Abstract: A process for producing poly(lactic acid)-based material includes a melt stretching step including melt stretching amorphous poly(lactic acid) resin at a melt stretch temperature Tms, wherein the amorphous poly(lactic acid) resin is capable of crystallization, and wherein the Tms is greater than the glass transition temperature Tg of the amorphous poly(lactic acid) resin and less than the crystallization temperature Tc of the amorphous poly(lactic acid) resin, thus providing a melt stretched poly(lactic acid); and a crystallization step including providing the melt stretched poly(lactic acid) at a cold crystallization temperature Tcc of greater than the glass transition temperature Tg of the amorphous poly(lactic acid) resin and less than the crystallization temperature Tc of the amorphous poly(lactic acid) resin, and wherein the melt stretched poly(lactic acid) is maintained at the cold crystallization temperature Tcc for a sufficient time tcc to allow for cold crystallization.

Abstract: Embodiments of the disclosure generally provide methods of using an interface protection layer disposed between an active layer and a source-drain metal electrode layer. In one embodiment, a method for forming an interface protection layer in a thin film transistor includes providing a substrate having an active layer formed thereon, wherein the active layer is a metal oxide layer, forming an interface protection layer on a portion of the active layer, and forming a source-drain electrode layer on the interface protection layer.

Abstract: The present invention relates to a rheometric device which provides a direct visualization of the subject material. The device also determines the velocity and/or the strain field across the thickness and the morphology to be determined across the same gap. The invention relates both to a device and/or method that can be used in connection with current shearing rheometers, and similar apparatus. The present invention also relates to a process for making a shear rate measurement. The invention provides versatility by allowing multiple angles of visualization which properly characterizes the flow characteristics and shear rates involved.

Abstract: The present invention is directed to an improved rheometer which provides direct visualization, and to a rheometer that can be used in conjunction with shearing devices, such as rotational, torsional, sliding plate, and other type rheometers.

Abstract: The present invention is directed to an improved rheometer which provides direct visualization, and to a rheometer that can be used in conjunction with shearing devices, such as rotational, torsional, sliding plate, and other type rheometers.

Abstract: The present invention is generally directed to a method for measuring interfacial stick-slip transitions (SST) and an improved constant-force shear capable of measuring interfacial SST. Some embodiments are capable of measuring SST under simple shear conditions and/or in highly entangled polymer melts. Some embodiments include the application of a constant shearing force to a polymer sample.

Abstract: The present invention relates to a rheometric device which provides a direct visualization of the subject material. The device also determines the velocity and/or the strain field across the thickness and the morphology to be determined across the same gap. The invention relates both to a device and/or method that can be used in connection with current shearing rheometers, and similar apparatus. The present invention also relates to a process for making a shear rate measurement. The invention provides versatility by allowing multiple angles of visualization which properly characterizes the flow characteristics and shear rates involved.

Abstract: The present invention is generally directed to a method for measuring interfacial stick-slip transitions (SST) and an improved constant-force shear capable of measuring interfacial SST. Some embodiments are capable of measuring SST under simple shear conditions and/or in highly entangled polymer melts. Some embodiments include the application of a constant shearing force to a polymer sample.

Abstract: The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.

Abstract: The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.

Abstract: The invention relates to cured dielectric films and a process for their manufacture which are useful in the production of integrated circuits. Dual layered dielectric films are produced in which a lower layer comprises a non-silicon containing organic polymer and an upper layer comprises an organic, silicon containing polymer. Such films are useful in the manufacture of microelectronic devices such as integrated circuits (IC's). In one aspect the upper layer silicon containing polymer has less than 40 Mole percent carbon containing substituents, and in another aspect it has at least approximately 40 Mole percent carbon containing substituents.

Abstract: The invention relates to cured dielectric films and a process for their manufacture which are useful in the production of integrated circuits. Dual layered dielectric films are produced in which a lower layer comprises a non-silicon containing organic polymer and an upper layer comprises an organic, silicon containing polymer. Such films are useful in the manufacture of microelectronic devices such as integrated circuits (IC's). In one aspect the upper layer silicon containing polymer has less than 40 Mole percent carbon containing substituents, and in another aspect it has at least approximately 40 Mole percent carbon containing substituents.

Abstract: The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.

Abstract: The invention relates to cured dielectric films and a process for their manufacture which are useful in the production of integrated circuits. Dual layered dielectric films are produced in which a lower layer comprises a non-silicon containing organic polymer and an upper layer comprises an organic, silicon containing polymer. Such films are useful in the manufacture of microelectronic devices such as integrated circuits (IC's). In one aspect the upper layer silicon containing polymer has less than 40 Mole percent carbon containing substituents, and in another aspect it has at least approximately 40 Mole percent carbon containing substituents.

Abstract: The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.

Abstract: A process for the preparation of substrates used in the manufacture of integrated circuits wherein spin-on low dielectric constant (low-k) polymer films are applied on semiconductor substrates. A non-etchback processing of spin-on low-k polymer films, without losing the low dielectric constant feature of the film, especially in between metal lines, is achieved utilizing electron beam radiation. A polymeric dielectric film is applied and dried onto a substrate and exposed to electron beam radiation under conditions sufficient to partially cure the dielectric layer. The exposing forms a relatively more hardened topmost portion of the dielectric layer and a relatively less hardened underlying portion of the dielectric layer.

Abstract: A screening process for ferroelectric memory devices that provides a greater degree of confidence in the mechanical and thermal stability of the ferroelectric material than prior art screening processes. A correspondingly higher degree of confidence in the reliability of the screened part results.