Abstract: A system and method for using scalable polynomials to translate a look-up table delay model into a memory efficient model. The system of the present invention receives an input library of predefined cells having a number of predefined look-up tables for modeling timing arcs through circuit paths of the cells. The present invention analyzes each memory inefficient look-up table and selects a polynomial form for representing the timing data of the look-up table. The polynomial form is selected from polynomial systems. For a particular selected polynomial form, the present invention performs a curve fitting analysis to determine the proper coefficients. The selected polynomial is then accepted or rejected based on a Chi-Square analysis. If accepted, the memory efficient polynomial replaces the look-up table. If rejected, a next polynomial form is selected and processing is re-done. If no acceptable polynomial form is found, the look-up table is not replaced.

Abstract: A system and method for using scalable polynomials to translate a look-up up table delay model into a memory efficient model. The system of the present invention receives an input library of predefined cells having a number of predefined look-up tables for modeling timing arcs through circuit paths of the cells. Each look-up table is referenced by two input variables (e.g., input transition rate and output load capacitance) which correspond to an output delay time. The present invention analyzes each memory inefficient look-up table and selects a polynomial form (of two variables) for representing the timing data of the look-up table. The polynomial form is selected from scalable polynomial systems (e.g., the decomposed Taylor Series and the Joint Taylor Series). The polynomial forms that are selected can have different orders (e.g., first, second, third, etc.) for the input variables.

Abstract: A computer system having a computer model of a Finite State Machine (FSM). The computer system includes a processor coupled to receive and manipulate the computer model, and a memory. The memory includes a computer model. The computer model includes, a first set of inputs, a first set of delayed inputs, a first set of outputs and a first set of delayed outputs. The computer model has a first output of the first set of outputs corresponding to a first input of the first set of inputs, a first delayed input of the first set of inputs and a first delayed output of the first set of delayed outputs.