Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

Abstract: A method, integrated circuit, and a computer readable medium that stores instructions for reducing IO traffic from a global or remote memory unit to a buffer of a neural network unit, by using overlap rows of an input feature map tile.

Abstract: A method for neural network convolution, the method may include receiving input data that is a 3D input data and comprises input data segments associated with different input data depth values; receiving a convolution kernel that is a 3D convolution kernel and comprises kernel segments associated with different kernel depth values; performing multiple 3D convolution iteration, wherein each of 3D convolution iteration comprises: determining whether the 3D convolution iteration is of a first type or of a second type; executing the 3D convolution iteration of the first type when determining that the 3D convolution iteration is of the first type; and executing the 3D convolution iteration of the second type when determining that the 3D convolution iteration is of the second type.