Abstract: Generating a design of an integrated circuit by analyzing a physical design of an integrated circuit by determining, for a pin of a circuit of the integrated circuit, that a candidate timing constraint for signal arrival time at the pin is later than a current timing constraint for signal arrival time at the pin, determining that a slack value associated with the current timing constraint has a greater negative value than a predefined negative slack threshold value, determining that the current timing constraint is within a user-defined range of signal arrival time values associated with the pin, determining that the candidate timing constraint is earlier than a latest-allowable signal arrival time at the pin, setting the current timing constraint equal to the candidate timing constraint, and generating a revised physical design of the integrated circuit that incorporates the current timing constraint.

Abstract: Zero wire load based assertions are generated. A zero wire load report is generated for a set of logic in a hardware description language corresponding to a circuit design. A set of assertions is identified for the circuit design by parsing the zero wire load report based in part on real data values corresponding to best case delays for one or more input pins and one or more output pins in a plurality of macros of the circuit design. A circuit may be fabricated based on the set of assertions.

Abstract: Generating a design of an integrated circuit by analyzing a physical design of an integrated circuit by determining, for a pin of a circuit of the integrated circuit, that a candidate timing constraint for signal arrival time at the pin is later than a current timing constraint for signal arrival time at the pin, determining that a slack value associated with the current timing constraint has a greater negative value than a predefined negative slack threshold value, determining that the current timing constraint is within a user-defined range of signal arrival time values associated with the pin, determining that the candidate timing constraint is earlier than a latest-allowable signal arrival time at the pin, setting the current timing constraint equal to the candidate timing constraint, and generating a revised physical design of the integrated circuit that incorporates the current timing constraint.

Abstract: A computer system for estimating timing convergence using assertion comparisons. The computer system receives predefined golden assertions associated with a macro to be tested. The computer system executes the macro to obtain current feedback assertion values. The computer system calculates one or more metrics based on a comparison between the current feedback assertion values and values of one or more different sets of assertions. The computer system estimates a time to convergence based on the one or more calculated metrics. The computer system generates a schedule based on the estimated time to convergence.

Abstract: Embodiments describing an approach to detecting negative paths for a circuit design based on a circuit timing test of the circuit design. Assigning each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design. Detecting a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws, and applying the modification to the circuit design to enable manufacturing an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.

Abstract: Zero wire load based assertions are generated. A zero wire load report is generated for a set of logic in a hardware description language corresponding to a circuit design. A set of assertions is identified for the circuit design by parsing the zero wire load report based in part on real data values corresponding to best case delays for one or more input pins and one or more output pins in a plurality of macros of the circuit design. A circuit may be fabricated based on the set of assertions.

Abstract: A computer system for estimating timing convergence using assertion comparisons. The computer system receives predefined golden assertions associated with a macro to be tested. The computer system executes the macro to obtain current feedback assertion values. The computer system calculates one or more metrics based on a comparison between the current feedback assertion values and values of one or more different sets of assertions. The computer system estimates a time to convergence based on the one or more calculated metrics. The computer system generates a schedule based on the estimated time to convergence.

Abstract: Embodiments describing an approach to detecting negative paths for a circuit design based on a circuit timing test of the circuit design. Assigning each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design. Detecting a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws, and applying the modification to the circuit design to enable manufacturing an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.

Abstract: Embodiments describing an approach to detecting negative paths for a circuit design based on a circuit timing test of the circuit design. Assigning each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design. Detecting a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws, and applying the modification to the circuit design to enable manufacturing an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.

Abstract: A computer system for estimating timing convergence using assertion comparisons. The computer system receives predefined golden assertions associated with a macro to be tested. The computer system executes the macro to obtain current feedback assertion values. The computer system calculates one or more metrics based on a comparison between the current feedback assertion values and values of one or more different sets of assertions. The computer system estimates a time to convergence based on the one or more calculated metrics. The computer system generates a schedule based on the estimated time to convergence.

Abstract: A computer system for estimating timing convergence using assertion comparisons. The computer system receives predefined golden assertions associated with a macro to be tested. The computer system executes the macro to obtain current feedback assertion values. The computer system calculates one or more metrics based on a comparison between the current feedback assertion values and values of one or more different sets of assertions. The computer system estimates a time to convergence based on the one or more calculated metrics. The computer system generates a schedule based on the estimated time to convergence.