Patents by Inventor Shiran Zhang

Shiran Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12342522
    Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, and forming a sacrificial dielectric layer on the substrate; patterning a part of the sacrificial dielectric layer along a first direction, and forming a plurality of first trenches arranged at intervals along a second direction in the sacrificial dielectric layer; patterning a part of the sacrificial dielectric layer at bottoms of the first trenches and a part of the substrate below the part of the sacrificial dielectric layer, and forming a plurality of second trenches arranged at intervals below the first trenches, wherein the second trench has a preset depth in the substrate; forming a protective layer on sidewalls of the first trenches and sidewalls of the second trenches; and forming bit line structures in the first trenches and the second trenches.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: June 24, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yang Chen, Xinru Han, Shiran Zhang
  • Patent number: 11843029
    Abstract: Embodiments of the present disclosure provide a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes: a base including an array region and a peripheral region, the peripheral region having a first isolation structure, the array region having a second isolation structure, a top opening area of the first isolation structure being greater than that of the second isolation structure; the first isolation structure having a first groove, and a first insulation structure configured to fill the first groove; and the first insulation structure including at least a top isolation layer, a top surface of the top isolation layer being flush with a top surface of the base, and the top isolation layer being made of at least a low dielectric constant material.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: December 12, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Youquan Yu, Gongyi Wu, Shiran Zhang
  • Publication number: 20230389264
    Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, and forming a sacrificial dielectric layer on the substrate; patterning a part of the sacrificial dielectric layer along a first direction, and forming a plurality of first trenches arranged at intervals along a second direction in the sacrificial dielectric layer; patterning a part of the sacrificial dielectric layer at bottoms of the first trenches and a part of the substrate below the part of the sacrificial dielectric layer, and forming a plurality of second trenches arranged at intervals below the first trenches, wherein the second trench has a preset depth in the substrate; forming a protective layer on sidewalls of the first trenches and sidewalls of the second trenches; and forming bit line structures in the first trenches and the second trenches.
    Type: Application
    Filed: January 6, 2023
    Publication date: November 30, 2023
    Inventors: Yang CHEN, Xinru Han, Shiran Zhang
  • Publication number: 20230050925
    Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple support structures on the substrate, where the multiple support structures are arranged at intervals along a first direction, and a gate trench is formed between every two adjacent support structures; forming a gate structure in the gate trench; and removing a part of each of the support structures, such that each of retained support structures forms two isolation sidewalls spaced apart, the two isolation sidewalls are arranged on opposite sidewalls of the adjacent gate structures respectively, and a filling region is formed by the two isolation sidewalls.
    Type: Application
    Filed: January 12, 2022
    Publication date: February 16, 2023
    Inventors: Xinru HAN, Yang CHEN, Shiran ZHANG
  • Publication number: 20220115385
    Abstract: The disclosure relates to a method for manufacturing a semiconductor device, a semiconductor device and a memory, and belongs to the field of semiconductor technologies. The method for manufacturing the semiconductor device includes: a semiconductor substrate is provided; a shallow trench isolation structure and a plurality of grooves arranged at intervals are formed on the semiconductor substrate, and a substrate bulge is formed between two adjacent grooves; a gate oxide layer is deposited on the surface of the semiconductor substrate, and the gate oxide layer covers the grooves and the substrate bulge; a gate structure is formed on the gate oxide layer, the gate structure includes a first gate structure and a second gate structure, and the first gate structure covers the surface of the substrate bulge; and a source electrode and a drain electrode are formed in the semiconductor substrate.
    Type: Application
    Filed: September 8, 2021
    Publication date: April 14, 2022
    Inventors: Shiran ZHANG, Zhengqing SUN, Youquan YU
  • Publication number: 20220102489
    Abstract: Embodiments of the present disclosure provide a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes: a base including an array region and a peripheral region, the peripheral region having a first isolation structure, the array region having a second isolation structure, a top opening area of the first isolation structure being greater than that of the second isolation structure; the first isolation structure having a first groove, and a first insulation structure configured to fill the first groove; and the first insulation structure including at least a top isolation layer, a top surface of the top isolation layer being flush with a top surface of the base, and the top isolation layer being made of at least a low dielectric constant material.
    Type: Application
    Filed: October 15, 2021
    Publication date: March 31, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Youquan YU, Gongyi WU, Shiran ZHANG
  • Publication number: 20200354291
    Abstract: A method of improving metathesis of an olefin can include introducing a promoter to an olefin feed stream.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Yuriy Roman, Shiran Zhang, Daniel Consoli, Sohel Shaikh