Patents by Inventor Shiraz Mohammad Zaman

Shiraz Mohammad Zaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for re-shuffling test case instruction orders for processor design verification and validation
    Patent number: 7669083
    Abstract: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sampan Arora, Sandip Bag, Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana, Shiraz Mohammad Zaman
  • System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation
    Publication number: 20090070631
    Abstract: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Inventors: Sampan Arora, Sandip Bag, Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Batchu Naga Venkata Satyanarayana, Shiraz Mohammad Zaman