Patents by Inventor Shirin Siddiqui
Shirin Siddiqui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090184348Abstract: Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.Type: ApplicationFiled: February 18, 2009Publication date: July 23, 2009Applicant: Texas Instruments IncorporatedInventors: Manoj Mehrotra, Karen Hildegard Ralston Kirmse, Shirin Siddiqui
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Patent number: 7510923Abstract: Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.Type: GrantFiled: December 19, 2006Date of Patent: March 31, 2009Assignee: Texas Instruments IncorporatedInventors: Manoj Mehrotra, Karen Hildegard Ralston Kirmse, Shirin Siddiqui
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Publication number: 20080145991Abstract: Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.Type: ApplicationFiled: December 19, 2006Publication date: June 19, 2008Inventors: Manoj Mehrotra, Karen Hildegard Ralston Kirmse, Shirin Siddiqui
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Patent number: 7344951Abstract: According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the drain region, and removing a second portion of the source region and the drain region by a plasma comprising a noble gas and oxygen.Type: GrantFiled: September 13, 2004Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventors: Patricia B. Smith, Majid M. Mansoori, Shirin Siddiqui
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Patent number: 7229869Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).Type: GrantFiled: March 8, 2005Date of Patent: June 12, 2007Assignee: Texas Instruments IncorporatedInventors: Jong Shik Yoon, Shirin Siddiqui, Amitava Chatterjee, Brian E. Goodlin, Karen H. R. Kirmse
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Patent number: 7132365Abstract: A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.Type: GrantFiled: August 10, 2004Date of Patent: November 7, 2006Assignee: Texas Instruments IncorporatedInventors: Sue Ellen Crank, Shirin Siddiqui, Deborah J. Riley, Trace Quentin Hurd, Peijun J. Chen
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Publication number: 20060205169Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).Type: ApplicationFiled: March 8, 2005Publication date: September 14, 2006Applicant: Texas Instruments IncorporatedInventors: Jong Yoon, Shirin Siddiqui, Amitava Chatterjee, Brian Goodlin, Karen Kirmse
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Patent number: 7018888Abstract: The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (100), among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having sidewall spacers (210 or 410) on opposing sidewalls thereof and placing source/drain implants (310, 510) into the substrate (110) proximate the gate structure (130). The method further includes removing at least a portion of the sidewall spacers (210 or 410) and annealing the source/drain implants (310, 510) to form source/drain regions (710) after removing the at least a portion of the sidewall spacers (210 or 410).Type: GrantFiled: July 30, 2004Date of Patent: March 28, 2006Assignee: Texas Instruments IncorporatedInventors: Brian E. Goodlin, Amitava Chatterjee, Shirin Siddiqui, Jong S. Yoon
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Publication number: 20060057810Abstract: According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the drain region, and removing a second portion of the source region and the drain region by a plasma comprising a noble gas and oxygen.Type: ApplicationFiled: September 13, 2004Publication date: March 16, 2006Inventors: Patricia Smith, Majid Mansoori, Shirin Siddiqui
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Publication number: 20060035463Abstract: A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non- thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.Type: ApplicationFiled: August 10, 2004Publication date: February 16, 2006Applicant: Texas Instruments IncorporatedInventors: Sue Crank, Shirin Siddiqui, Deborah Riley, Trace Hurd, Peijun Chen
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Publication number: 20060024872Abstract: The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (100), among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having sidewall spacers (210 or 410) on opposing sidewalls thereof and placing source/drain implants (310, 510) into the substrate (110) proximate the gate structure (130). The method further includes removing at least a portion of the sidewall spacers (210 or 410) and annealing the source/drain implants (310, 510) to form source/drain regions (710) after removing the at least a portion of the sidewall spacers (210 or 410).Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Applicant: Texas Instruments, IncorporatedInventors: Brian Goodlin, Amitava Chatterjee, Shirin Siddiqui, Jong Yoon