Abstract: Apparatuses, systems, and techniques for managing memory devices. In at least one embodiment, a processor is provided to assign personalities to one or more memory devices.

Abstract: Methods, devices, systems, and computer program products to provide a hybrid pipelined-data flow packet processing architecture by normalizing sequential and parallel data paths along with scaling in network compute and stateful network flows. The method includes receiving state data, policy data, scheduling data, and/or dataflow operation data. The method also includes processing data packets based on configured or dynamically updated states, policies, scheduling, and dataflow operations. The method includes performing arithmetic logic unit (ALU)/program execution operations on the data packets based on incoming and outgoing data and control planes. The method also includes intelligently configuring a packet processing flow based on at least one of the state data, the priority data, the scheduling data, and the dataflow operation data.

Abstract: Apparatuses, systems, and techniques to allocate portions of a virtual address space to allow virtual machines to share data. In at least one embodiment, at least a portion of a virtual memory address space is made accessible to multiple virtual machines and is mapped to memory addresses of different physical devices using, at least in part, a cache-coherent protocol.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is to be logically organized with a namespace divided into two or more zones, determine two or more different zone size dependent parameters associated with the two or more persistent storage devices, determine a smallest aligned boundary based on each of the two or more different zone size dependent parameters, and set a zone group size for access to the two or more persistent storage devices based on the determined smallest aligned boundary. Other embodiments are disclosed and claimed.

Abstract: Apparatuses, systems, and techniques to deceive a sender of a communication and optionally use that deception to gather data associated with the sender and/or the communication.

Abstract: In at least one embodiment, a solid state storage device (“SSD”) service provider provides an application programming interface (“API”) that allows an application to specify a first personality type for the requested SSD. In at least one embodiment, the SSD service provider provides an API of the requested type, but may fulfil the request using an SSD having a second SSD personality type by translating calls from the first SSD personality type to the second SSD personality type.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is to be logically organized with a namespace divided into two or more zones, determine two or more different zone size dependent parameters associated with the two or more persistent storage devices, determine a smallest aligned boundary based on each of the two or more different zone size dependent parameters, and set a zone group size for access to the two or more persistent storage devices based on the determined smallest aligned boundary. Other embodiments are disclosed and claimed.

Abstract: Apparatuses, systems, and techniques to allocate portions of a virtual address space to allow virtual machines to share data. In at least one embodiment, at least a portion of a virtual memory address space is made accessible to multiple virtual machines and is mapped to memory addresses of different physical devices using, at least in part, a cache-coherent protocol.

Abstract: A host Flash Translation Layer (FTL) synchronizes host FTL operations with the drive FTL operations to reduce write amplification and over-provisioning. Embodiments of FTL synchronization map, at the host FTL software (SW) stack level, logical bands in which data is managed, referred to as host bands, to the physical bands on a drive where data is stored. The host FTL tracks validity levels of data managed in host bands to determine validity levels of data stored in corresponding physical bands, and optimizes defragmentation operations (such as garbage collection processes and trim operations) applied by the host FTL SW stack to the physical bands based on the tracked validity levels.

Abstract: A processing device in a memory sub-system identifies a stream of data that is associated with an exclusive-or (XOR) calculator component generating first parity data for data from the stream of data that is stored in a memory sub-system. The processing device further receives one or more characteristics associated with the stream of data, and assigns the stream of data to a buffer memory of the XOR calculator component based on the received one or more characteristics.

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to read utilization-related information for a resource from a memory shared with a processor in response to a request from the processor for the resource, and schedule utilization of the resource based at least in part on the utilization-related information for the resource. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, maintain respective read disturb (RD) counters for each of two or more tracked units at respective granularities, maintain respective global RD counters for each of the two or more tracked units and, in response to a read request, increment one or more global RD counters that correspond to the read request, determine if a global RD counter for a tracked unit matches a random number associated with the tracked unit and, if so determined, increment a RD counter for the tracked unit that corresponds to the read request and generate a new random number for the tracked unit. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses and methods provide for a memory controller to manage quality of service enforcement. For example, a memory controller includes logic to determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis. The projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters. A requested bandwidth level and a requested quality of service level is received from a host in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels.

Abstract: A method is described. The method includes tracking a logical saturation value for each of multiple streams having read and write commands directed to a mass storage device, wherein, a stream's logical saturation value is a measurement of how much of the stream's assigned storage resources of the mass storage device contains valid data. The method also includes repeatedly selecting for garbage collection whichever of the multiple streams has a lowest logical saturation value as compared to the other streams.

Abstract: An embodiment of a semiconductor apparatus may include technology to provide placement option information to a host in response to a host query, and create a namespace to access a persistent storage media based on host-provided isolation granularity information. Other embodiments are disclosed and claimed.

Abstract: A processing device in a memory sub-system identifies a stream of data that is associated with an exclusive-or (XOR) calculator component generating first parity data for data from the stream of data that is stored in a memory sub-system. The processing device further receives one or more characteristics associated with the stream of data, and assigns the stream of data to a buffer memory of the XOR calculator component based on the received one or more characteristics.

Abstract: A request to read data stored in a non-volatile memory (NVM) is processed by incrementing a global read counter for the NVM, incrementing a local read counter for a zone of the NVM being accessed by processing of the read request, computing a degree of read hotness for the zone, computing a read concentration of the zone based at least in part on the degree of read hotness of the zone, the global read counter, and the local read counter, and relocating the data in the NVM when the read concentration of the zone meets or exceeds a threshold.

Abstract: A buffer memory storing first parity data for a first stream of data associated with data that is stored at a storage system may be identified. A request to store second parity data for a second stream of data associated with data that is to be stored at the storage system may be received and a characteristic of the first stream of data may be identified. A determination may be made as to whether to replace the first parity data for the first stream with the second parity data for the second stream based on the characteristic of the first stream of data. In response to determining to replace the first parity data with the second parity data based on the characteristic, the second parity data for the second stream of data may be generated and stored at the buffer memory to replace the first parity data.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is to be logically organized with a namespace divided into two or more zones, determine two or more different zone size dependent parameters associated with the two or more persistent storage devices, determine a smallest aligned boundary based on each of the two or more different zone size dependent parameters, and set a zone group size for access to the two or more persistent storage devices based on the determined smallest aligned boundary. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage device which is logically organized with a namespace divided into two or more zones, receive a write request for a first zone of the two or more zones of the namespace, determine if the first zone can accommodate the write request, and span the write request across a second zone of the two or more zones of the namespace if the first zone cannot accommodate the write request. Other embodiments are disclosed and claimed.