Abstract: This disclosure provides systems, methods and apparatuses for intelligent connectivity switching techniques. The techniques include, for example, determining that a wireless connection is encrypted, and in response to determining that the wireless connection is encrypted, employing one or more intelligent connectivity switching mechanisms to ensure a desirable level of user experience may be maintained and data stall conditions may be avoided or overcome. When a wireless station is in an area where two radio access technology (RAT) connections are present, the intelligent connectivity switching mechanisms can include responding to a user interface prompt, evaluating one or more signal-to-noise (SNR)-related metrics, or comparing an application, task or activity to a whitelist.

Abstract: This disclosure provides systems, methods and apparatuses for intelligent connectivity switching techniques. The techniques include, for example, determining that a wireless connection is encrypted, and in response to determining that the wireless connection is encrypted, employing one or more intelligent connectivity switching mechanisms to ensure a desirable level of user experience may be maintained and data stall conditions may be avoided or overcome. When a wireless station is in an area where two radio access technology (RAT) connections are present, the intelligent connectivity switching mechanisms can include responding to a user interface prompt, evaluating one or more signal-to-noise (SNR)-related metrics, or comparing an application, task or activity to a whitelist.

Abstract: Systems and methods for dynamically adjusting an input parameter, such as power supply level, to a shared power domain in a portable computing device are disclosed. The power domain includes a plurality of processing resources that share the power source. The power supply level is reduced based on a critical core vote pool derived from votes from the plurality of processing resources. The critical core vote pool is narrowed from all the votes by disqualifying votes based on the operating status of the associated processing resources. For example, because inactive processing resources may be unaffected by a change in the voltage level to the shared domain, and because certain active processing resources are in a position to adjust to a power change dictated by another processing resource, such processing resources may be considered noncritical and their votes disqualified from consideration.

Abstract: A method and computing apparatus for controlling operation of hardware processing components are disclosed. The method may include receiving a data packet (e.g., a media frame) at the computing device, processing the data packet with a plurality of hardware components to display the data packet, and monitoring movement of the data packet among the hardware components. A time indication for each hardware component is generated that indicates when the data packet will be received, and a frequency of each of the hardware components is adjusted based upon when the frame will arrive to be processed.

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

Abstract: Systems and methods for dynamically adjusting an input parameter to a power domain in a portable computing device are disclosed. The power domain includes two or more processing resources that share a power source. Dynamic use of the two or more processing resources creates an opportunity to adjust the input parameter when a status change associated with a processing resource in the power domain occurs. A controller in the power domain includes logic that responds to a status indicator associated with a respective processing resource in the power domain by generating a control signal that directs a device to adjust one or both of input voltage and clock frequency.

Abstract: This disclosure describes systems, methods, and apparatus for reducing power consumption and improving performance on a computing device. A method includes scheduling, with a driver on the computing device, one or more activity times that indicate when the driver will be active and storing the one or more activity times that indicate when the driver will be active. When a request to suspend a system of the computing device is received, the stored activity times are accessed to identify when the driver will be active, and a determination is made whether any of the one or more activity times is scheduled to occur within a suspend time window. If the driver will not be active during the suspend time window, suspension of the system is initiated.

Abstract: A method and apparatus for adjusting buffer size are provided. The method may comprise downloading a media file onto a media-player device, and then detecting, by the media-player device, the speed of the downloading. The method may further comprise transferring a first buffer packet of media content from the media file to a media processor. Then, the method may comprise providing and interrupt signal from the media processor, that indicated that the media content of first buffer packet has reached a lower media content threshold, and transferring, to the media processor, in response to the interrupt signal, one or more variably-sized buffer packets that are adjusted in size based on the speed of the downloading.

Abstract: This disclosure describes systems, methods, and apparatus for reducing power consumption and improving performance on a computing device. A method includes scheduling, with a driver on the computing device, one or more activity times that indicate when the driver will be active and storing the one or more activity times that indicate when the driver will be active. When a request to suspend a system of the computing device is received, the stored activity times are accessed to identify when the driver will be active, and a determination is made whether any of the one or more activity times is scheduled to occur within a suspend time window. If the driver will not be active during the suspend time window, suspension of the system is initiated.

Abstract: A method and computing apparatus for controlling operation of hardware processing components are disclosed. The method may include receiving a data packet (e.g., a media frame) at the computing device, processing the data packet with a plurality of hardware components to display the data packet, and monitoring movement of the data packet among the hardware components. A time indication for each hardware component is generated that indicates when the data packet will be received, and a frequency of each of the hardware components is adjusted based upon when the frame will arrive to be processed.

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

Abstract: Systems and methods for managing communications on a communication device are disclosed. A method may include receiving a communication packet at the communication device via a network connection and determining, at the communication device, whether the communication packet is an unsolicited control packet. Dormancy of the network connection is triggered after a first time period if the communication packet is not an unsolicited control packet, and dormancy of the network connection is triggered after a second time period if the communication packet is an unsolicited control packet wherein the second time period is less than the first time period.

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

Abstract: Systems and methods for dynamically adjusting an input parameter, such as power supply level, to a shared power domain in a portable computing device are disclosed. The power domain includes a plurality of processing resources that share the power source. The power supply level is reduced based on a critical core vote pool derived from votes from the plurality of processing resources. The critical core vote pool is narrowed from all the votes by disqualifying votes based on the operating status of the associated processing resources. For example, because inactive processing resources may be unaffected by a change in the voltage level to the shared domain, and because certain active processing resources are in a position to adjust to a power change dictated by another processing resource, such processing resources may be considered noncritical and their votes disqualified from consideration.

Abstract: The present disclosure relates to synchronization and parallel operation of two or more cores within a multi-core computing system so as to reduce an amount of time that all cores are operating during a processing period and thereby increase an amount of idle time per processing period. In this way deeper sleep and/or idle states for the cores and the system can be entered.

Abstract: An enhanced OnDemand Governor is disclosed that computes a steady-state frequency based on prior recommended CPU frequencies and applies a steady-state frequency when available. When not available, a turbo frequency or a computed lower frequency is applied. For increased loads, the steady-state frequency can be applied for one or more cycles until it becomes apparent that gradual frequency increases are not sufficient to meet a large CPU load, at which point the turbo frequency is applied and the history of CPU frequencies can be flushed. The enhanced OnDemand Governor can be turned on where periodic loads are detected while the traditional OnDemand Governor can be used in all other use cases.

Abstract: Systems and methods for dynamically adjusting an input parameter to a power domain in a portable computing device are disclosed. The power domain includes two or more processing resources that share a power source. Dynamic use of the two or more processing resources creates an opportunity to adjust the input parameter when a status change associated with a processing resource in the power domain occurs. A controller in the power domain includes logic that responds to a status indicator associated with a respective processing resource in the power domain by generating a control signal that directs a device to adjust one or both of input voltage and clock frequency.

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.