Patents by Inventor Shiro Akamatsu
Shiro Akamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240129626Abstract: An appropriate user interface corresponding to a use state of an apparatus is provided. An imaging system includes an imaging apparatus and an information processing apparatus. The imaging apparatus has a control related to an imaging operation performed based on an operation input performed in the information processing apparatus by connecting to the information processing apparatus by using wireless communication. The information processing apparatus performs a control for switching a display state of a display screen related to an imaging operation of the imaging apparatus, based on a connection number of imaging apparatuses and information processing apparatuses connected by using wireless communication.Type: ApplicationFiled: October 4, 2023Publication date: April 18, 2024Inventors: Ryogo Ito, Shiro Eshita, Megumi Takagi, Kazuma Akamatsu, Ayumi Yamamoto
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Patent number: 7560752Abstract: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.Type: GrantFiled: January 7, 2008Date of Patent: July 14, 2009Assignee: Nichia CorporationInventors: Shiro Akamatsu, Yuji Ohmaki
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Patent number: 7459718Abstract: A FET includes a nitride semiconductor in which leak current is reduced and breakdown voltage is improved. The FET is formed from a substrate, a buffer layer made of a nitride semiconductor, a first semiconductor layer made of a nitride semiconductor, and a second semiconductor layer made of a nitride semiconductor, wherein at least the buffer layer and the first semiconductor layer include a p-type dopant. The concentration of the p-type dopant is higher in the buffer layer than that in the first semiconductor layer, and the concentration of the p-type dopant is higher in the first semiconductor layer than that in the second semiconductor layer.Type: GrantFiled: March 22, 2006Date of Patent: December 2, 2008Assignee: Nichia CorporationInventors: Mitsuo Hayamura, Shiro Akamatsu
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Publication number: 20080135854Abstract: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.Type: ApplicationFiled: January 7, 2008Publication date: June 12, 2008Inventors: Shiro Akamatsu, Yuji Ohmaki
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Patent number: 7339206Abstract: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.Type: GrantFiled: March 24, 2006Date of Patent: March 4, 2008Assignee: Nichia CorporationInventors: Shiro Akamatsu, Yuji Ohmaki
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Publication number: 20060231861Abstract: An FET includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.Type: ApplicationFiled: March 24, 2006Publication date: October 19, 2006Applicant: NICHIA CORPORATIONInventors: Shiro Akamatsu, Yuji Ohmaki
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Publication number: 20060214193Abstract: A FET includes a nitride semiconductor in which leak current is reduced and breakdown voltage is improved. The FET is formed from a substrate, a buffer layer made of a nitride semiconductor, a first semiconductor layer made of a nitride semiconductor, and a second semiconductor layer made of a nitride semiconductor, wherein at least the buffer layer and the first semiconductor layer include a p-type dopant. The concentration of the p-type dopant is higher in the buffer layer than that in the first semiconductor layer, and the concentration of the p-type dopant is higher in the first semiconductor layer than that in the second semiconductor layer.Type: ApplicationFiled: March 22, 2006Publication date: September 28, 2006Applicant: NICHIA CORPORATIONInventors: Mitsuo Hayamura, Shiro Akamatsu
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Patent number: 6423584Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode. A hole for connecting between the two layers of the gate electrode of a first field-effect transistor used as perpheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting between the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode.Type: GrantFiled: March 20, 2001Date of Patent: July 23, 2002Assignee: Hitachi, Ltd.Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
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Patent number: 6420754Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells. A hole for connecting the two layers of the gate electrode of a first field-effect transistor used as peripheral circuit is provided at a location which two-dimensionally overlaps the active area within the plane of the gate electrode, and a hole for connecting the two layers of the gate electrode of a second field-effect transistor used as a peripheral circuit is provided at a location which two-dimensionally overlaps an isolation area within the plane of the gate electrode. The gate length of the first field-effect transistor is longer than the gate length of the second field-effect transistor, and the gate width of the first field-effect transistor is wider than the gate width of the second field-effect transistor.Type: GrantFiled: February 26, 2001Date of Patent: July 16, 2002Assignee: Hitachi, Ltd.Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
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Publication number: 20010024859Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode.Type: ApplicationFiled: March 20, 2001Publication date: September 27, 2001Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato
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Publication number: 20010020718Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode.Type: ApplicationFiled: February 26, 2001Publication date: September 13, 2001Inventors: Masahito Takahashi, Shiro Akamatsu, Akihiko Satoh, Fukuo Owada, Masataka Kato