Abstract: A method for distinguishing prostate cancer from prostatic hypertrophy using the method for analyzing PSA and an analysis kit of PSA are provided. An object of the present invention can be solved by being brought into contact a lectin having an affinity for p-N-acetylgalactosamine residues and/or a lectin having an affinity for fucose a(I, 2) galactose residues with a sample possibly containing PSA, to determine an amount of PSA having an affinity for the lectin. A method for distinguishing prostate cancer from prostatic hypertrophy can be provided by this method.

Abstract: A method for distinguishing prostate cancer from prostatic hypertrophy using the method for analyzing PSA and an analysis kit of PSA are provided. An object of the present invention can be solved by being brought into contact a lectin having an affinity for ?-N-acetylgalactosamine residues and/or a lectin having an affinity for fucose ?(1, 2) galactose residues with a sample possibly containing PSA, to determine an amount of PSA having an affinity for the lectin. A method for distinguishing prostate cancer from prostatic hypertrophy can be provided by this method.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.