Abstract: A semiconductor storage device having a word line driving circuit of a small circuit scale, and operating in stability. The device includes a first driving circuit 11 for driving a word line driving signal 15 towards a first potential, a second driving circuit 12 for driving the word line driving signal 15 towards a second potential, a third driving circuit 13 for driving the word line driving signal 15 to a third potential, and a driving control circuit 14. This driving control circuit 14 actuates the first driving circuit 11 when the input signal 16 is at a first logical value, while actuating the second driving circuit 12 when the input signal 16 transfers from the first logical value to the second logical value and actuating the third driving circuit 13 on detection that the word line driving signal 15 has been driven towards the second potential.

Abstract: A redundancy control circuit includes a plurality of program elements and a voltage control section. In the plurality of program elements, a defect address indicating a position of a defect is programmed by a dielectric breakdown due to applying of a voltage. The voltage control section applies the voltage to a part of a plurality of targeted program elements simultaneously. The plurality of targeted program elements is a part of the plurality of program element to be dielectrically broken down correspondingly to the defect address.

Abstract: A semiconductor storage device having a word line driving circuit of a small circuit scale, and operating in stability. The device includes a first driving circuit 11 for driving a word line driving signal 15 towards a first potential, a second driving circuit 12 for driving the word line driving signal 15 towards a second potential, a third driving circuit 13 for driving the word line driving signal 15 to a third potential, and a driving control circuit 14. This driving control circuit 14 actuates the first driving circuit 11 when the input signal 16 is at a first logical value, while actuating the second driving circuit 12 when the input signal 16 transfers from the first logical value to the second logical value and actuating the third driving circuit 13 on detection that the word line driving signal 15 has been driven towards the second potential.

Abstract: A redundancy control circuit includes a plurality of program elements and a voltage control section. In the plurality of program elements, a defect address indicating a position of a defect is programmed by a dielectric breakdown due to applying of a voltage. The voltage control section applies the voltage to a part of a plurality of targeted program elements simultaneously. The plurality of targeted program elements is a part of the plurality of program element to be dielectrically broken down correspondingly to the defect address.

Abstract: A method is disclosed for remedying defective cells that enables automatic cutting of capacitor fuses as part of the fabrication process. A comparison circuit determines whether defective cells are present in a memory cell array by comparing data that have been read from an I/O bus with data that have been determined in advance to determine whether the data are identical and supplies the determination result as a determination signal. An address buffer circuit, upon receiving a determination signal from the comparison circuit, latches the row address signal and column address signal that are being supplied as output at that time and supplies these latched signals as a capacitor fuse row address signal and a capacitor fuse column address signal for cutting capacitor fuses. Capacitor fuses in a capacitor fuse block are then each cut based on the capacitor fuse row/column address signals that have been latched by the address buffer circuit.

Abstract: A method is disclosed for remedying defective cells that enables automatic cutting of capacitor fuses as part of the fabrication process. A comparison circuit determines whether defective cells are present in a memory cell array by comparing data that have been read from an I/O bus with data that have been determined in advance to determine whether the data are identical and supplies the determination result as a determination signal. An address buffer circuit, upon receiving a determination signal from the comparison circuit, latches the row address signal and column address signal that are being supplied as output at that time and supplies these latched signals as a capacitor fuse row address signal and a capacitor fuse column address signal for cutting capacitor fuses. Capacitor fuses in a capacitor fuse block are then each cut based on the capacitor fuse row/column address signals that have been latched by the address buffer circuit.

Abstract: A semiconductor storage device (100) is disclosed that includes sense amplifier rows (SA0 to SA16) that receive a common sense amplifier drive voltage VINTA supplied by a internal voltage driver (5) having a high current source mode. According to one embodiment, the semiconductor storage device (100) may include banks of memory cells (B0 to B15), row decoders (DC0 to DC15), bank enable generation circuits (EC0 to EC15), sense amplifier rows (SA0 to SA16), sense amplifier drivers (DRA0 to DRA16), sense amplifier control circuits (SCA0 to SCA16), and internal voltage drivers (5 and 6). Internal voltage driver (5) can include a high current source or high voltage source mode, which can be received by a sense amplifier row (SA0 to SA16) during predetermined initial sense period. Other sense amplifier rows (SA0 to SA16) having already sensed data can be isolated from internal voltage driver (5) during the high current source or high voltage source mode.

Abstract: A semiconductor storage device (100) is disclosed that includes sense amplifier rows (SA0 to SA16) that receive a common sense amplifier drive voltage VINTA supplied by a internal voltage driver (5) having a high current source mode. According to one embodiment, the semiconductor storage device (100) may include banks of memory cells (B0 to B15), row decoders (DC0 to DC15), bank enable generation circuits (EC0 to EC15), sense amplifier rows (SA0 to SA16), sense amplifier drivers (DRA0 to DRA16), sense amplifier control circuits (SCA0 to SCA16), and internal voltage drivers (5 and 6). Internal voltage driver (5) can include a high current source or high voltage source mode, which can be received by a sense amplifier row (SA0 to SA16) during predetermined initial sense period. Other sense amplifier rows (SA0 to SA16) having already sensed data can be isolated from internal voltage driver (5) during the high current source or high voltage source mode.

Abstract: A semiconductor memory device having a plurality of memory blocks, each block including a plurality of memory banks, which can be accurately operated with high speed, and which consumes less power. The device includes a row decoding section for decoding the row address to generate a row selecting signal, and a column decoding section, adjacent to the row decoding section, for decoding the column address to generate a column selecting signal. The word lines driven by the row selecting signal and column selecting signal lines for outputting the column selecting signal are arranged parallel to each other to supply these signals to the memory block of a target memory cell and to access the memory cell.

Abstract: A voltage circuit for a device having an active period and an inactive period comprises a reference voltage generator generating a reference voltage and a voltage stabilizer receiving the reference voltage. The voltage stabilizer includes first circuit componentry for raising a potential of an output terminal during the active period of the device and second circuit componentry for lowering a potential of the output terminal during at least the inactive period of the device.

Abstract: A bonding option circuit comprises a logic gate circuit connected between a bonding pad and a power supply voltage, a load capacitance connected between ground and the logic gate circuit, and an output stabilizer circuit having an input connected to the bonding pad and an output connected to an output terminal. The logic circuit is so configured that when the bonding pad is in a floating condition, the logic circuit connects the bonding pad to the power supply voltage, and when the bonding pad is bonded to the ground, the logic circuit disconnects a current path between the bonding pad and the power supply voltage.

Abstract: A redundant control circuit compares a defective address with an external address to determine whether a redundant word line is driven for a read-out operation instead of a defective word line assigned as a defective address, and keeps a redundant control signal on a precharged output signal line at an active high voltage level in the presence of the external address consistent with the defective address. A precharging unit not only charges the output signal line to the active high voltage level before arrival of the external address but also keeps the output signal line at the active high voltage level even if a current path is undesirably established from the output signal line to a discharge line in the presence of the external address consistent with the defective address, thereby preventing the defective word line from being undesirably accessed.