Abstract: An arbiter performs activation of memory that corresponds to a bus access request from DSP in parallel with an access to memory that corresponds to a bus access request from CPU, when DSP requests to access the bus before the access to memory that corresponds to the bus access request from CPU has been completed. Therefore, immediately after the access to memory that corresponds to the bus access request from CPU has been completed, the access to memory that corresponds to the bus access request from DSP is allowed, thereby improving processing performance.

Abstract: A test apparatus has a scan path consisting of scan flip-flops connected in a shift register fashion. Any two adjacent scan flip-flops include clock generating circuits for generating clock signals for shifting scan data at a rising edge and a falling edge of the clock signals in a test scan mode, respectively. Each clock generating circuit further includes a scan flag generator for generating a scan flag for halting the clock signal of the scan flip-flop. The test apparatus can prevent a hold error due to clock skew without complicating the design process, and with a simple circuit configuration.

Abstract: A block to raster converting circuit which is adaptable to all formats with a single circuit is realized. Macro-block data is mapped into a frame memory (13) on the basis of a particular format whose data size (X) in the horizontal direction provides a max condition. When writing, for each macro-block row (MBRi), the address of the first data in the initial macro-block (IMBi) is specified, on the basis of which address the column and row addresses are regularly switched according to the data array in the macro-block (MB). When reading, for each macro-block row (MBRi), the address of the initial data is specified, on the basis of which address the row address is switched every time data in each horizontal line in the macro-block row (MBRi) has been read and every time data at a turn of the column address in the frame memory (13) has been read. The column address is sequentially switched.

Abstract: A decoder for converting packet data into raster data is provided. The packet data includes data about a picture-compressed video signal and data about a picture format including a picture rate. The decoder comprising a first processing means, second processing means and a storage means. The first processing means converts the packet data into intermediate data such that picture compression is eliminated from the picture-compressed video signal and outputs the intermediate data. The second processing means receives the intermediate data from the first processing means and processes the intermediate data to output raster data for one frame at a frame frequency. The storage means stores the intermediate data for processing the intermediate data in the second processing means. The second processing means writes the intermediate data into the storage means at a frequency related to the picture rate and reads the raster data for one frame from the storage means at the frequency equal to the frame frequency.

Abstract: An output from an adder 10.sub.1, i.e., an output of a first bit plane is inputted to an adder 10.sub.6 through delay elements 2.sub.2 and 3.sub.0 and a multiplier 100.sub.0. On the other hand, input data X are inputted to multipliers C.sub.2.sup.1 to C.sub.0.sup.1 through a delay element 1.sub.0 and multiplied by the respective multipliers to obtain partial products. An adder 10.sub.2 receives a partial product by the multiplier C.sub.2.sup.1 through a delay element 2.sub.3 and a partial product by the multiplier C.sub.1.sup.1. An adder 10.sub.3 receives an output from the adder 10.sub.2 through the delay element 2.sub.3 and on the other hand a partial product by the multiplier C.sub.0.sup.1. An output from the adder 10.sub.3, i.e., an output of a second bit plane is inputted to the adder 10.sub.6 through a delay element 2.sub.5. The adder 10.sub.6 performs addition of the output from the adder 10.sub.3, i.e., the output of the second bit plane and the output from the adder 10.sub.1, i.e.

Abstract: The function of a line memory can be achieved only with one bit line. As word lines WL.sub.j-1 and WL.sub.j are activated in this order, data has already been read out before new data is written into memory cells MC.sub.j-1,i and MC.sub.j,1. More specifically, a writing process is performed on the same memory cell after a readout process, achieving delay operation as taught in a conventional technique. Further, as both operations of a tristate buffer 11 and a D latch 13 are controlled in accordance with the readout and the writing processes, one bit line serves both as a write bit line and a read bit line.

Abstract: A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.

Abstract: Dummy information of a third level, which is between first and second levels written in a plurality of memory cells, is written in a dummy memory cell from a source node through transistors. Thus, a potential difference is caused between a read bit line and a dummy read bit line in reading. A potential comparison circuit indicates the level of information read from any memory cell on the basis of the comparison result as to the potentials of the dummy read bit line and the read bit line. Thus, the read rate is increased, the read operation is stabilized and increase of the chip area is suppressed.

Abstract: In an FIFO memory, a word line pointer (4) sequentially specifies word lines (8) in accordance with the first clock signal (CLK1) outputted from a clock generator (3). When the last pointer (5) outputs a last line access signal (PAS3) indicating that the last word line (8E) has been accessed, a control flag generator (2) detects that the last address has been accessed on the basis of the last line access signal (PAS3) and a clock signal (COS) in synchronization with the first clock (CLK1) and outputs a clock control signal (CCNT) in accordance with a timing of the detection. The clock generator 3 stops counting a reference clock signal (CLK0) in response to the clock control signal (CCNT). Thus, the access to a memory cell array of the FIFO memory is stopped in accordance with the number of effective pixels of inputted video signals, and thereby reduction in memory capacity and in power consumption can be achieved.

Abstract: y memory blocks are connected in series. A row select signal is output to each memory block from a row address pointer corresponding to a plurality of memory circuits in one memory block. Similarly, a column select signal is output to each memory block from a column address pointer corresponding to a plurality of memory circuits in one memory block. Therefore, the same row and column select signals are applied to each memory block, whereby data is sequentially input/output for every memory block. Thus, the circuit complexity of the row and column address pointers can be reduced.

Abstract: A current source circuit according to the present invention is provided with an output terminal 100, a bias voltage source 21, N channel MOS transistors 2 and 1 and P channel MOS transistor 3. The source of transistor 2, the drain of transistor 1 and the drain of transistor 3 are connected to a common node, the drain of transistor 2 is connected to output terminal 100 and the gate of transistor 2 is connected to bias voltage source 21. Conductions of transistors 1 and 3 are dynamically controlled in response to an external signal. As a result, it is possible to implement a current source circuit having a small number of devices and enabling an operation at a high speed.

Abstract: An improved serial-parallel type A/D converter is disclosed herein. A gate circuit 7 applies signals S11' to S14' provided from an encoder 3 only in a fine comparison period to switching circuits 11 to 14 as switching control signals S11 to S14. In the fine comparison period, one switching circuit is turned on, so that a fine comparison voltage is applied to voltage comparators 21 to 23. Since all of the switching circuits are turned off in a coarse comparison period, correct coarse comparison voltage is provided from a reference voltage generating circuit. As a result, a correct conversion in the coarse comparison period can be performed.

Abstract: Low-order reference potentials including high-order reference potentials (VRT, VRB, VC0 to VC6) generated from a ladder resistor and potentials (V(i, j) (i=0 to 7, j=0 to 6)) are applied to potential lines, respectively, to be transmitted by various switches to analog bus lines (FR0a to FR14a) or analog bus lines (FR0b FR14b). The low-order reference potentials are applied to the analog bus lines (FR0b to FR14b) when it is judged that a sample signal potential falls in voltage zones (Z0 to Z3) as a result of comparison with the high-order reference potentials and are applied to the analog bus lines (FR0a to FR14a) when it is judged that the sample signal potential falls in voltage zones (Z4 to Z7). This provides for reduction in the number of switches connected to each analog bus line and in parasitic capacitance, so that a settling time of the low-order reference potentials is shortened. High-speed operation of a series-parallel A-D converter is achieved.

Abstract: An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

Abstract: A voltage comparator for use in a subranging A/D converter includes a coarse preceding comparison circuit 30, a fine preceding comparison circuit 31, and an amplification circuit 32 having an automatic zero compensation function. The coarse preceding comparison circuit 30 compares an analog input voltage Vin and a coarse reference voltage Vai. The fine preceding comparison circuit 31 compares the analog input voltage Vin and a fine reference voltage Vbi. The coarse and fine preceding comparison circuits 30, 31 sequentially outputs comparison results to the amplification circuits 32 so that the comparison results do not overlap each other. The amplification circuits 32 resets offset voltages before amplifying the comparison results applied. The number of elements necessary for a subranging A/D converter can be reduced, and a voltage comparator operating at a high speed and highly accurately can be provided.

Abstract: An A/D converter includes a resistor network generating a reference voltage, a level detector for detecting the level of an input analogue signal with a reference voltage from the resistor network as a reference, and an encoder for providing a digital signal by encoding the output of the level detector. The level detector includes a plurality of comparators for bilevel-processing the input analogue signal with a preselected voltage from the resistor connection nodes of the resistor network as a reference voltage. The resistor network comprises a plurality of resistor elements between a first node receiving a first reference voltage and a second node receiving a second reference voltage, which are interconnected to provide a voltage from an associated connection node that is 1/2.sup.j times the difference between said first reference voltage and said second reference voltage.

Abstract: A reference voltage generating circuit is disclosed which generates a plurality of linear analog voltages and is desirably applied to A/D and D/A converters. As the reference voltage generating circuit itself or a resistor network comprised therein, a resistor network is employed which comprises a plurality of resistor elements connected in series between two power sources and resistor networks (or resistor elements) connected to all the other nodes than the two nodes closest to the two power sources, respectively, out of the nodes between the former resistor elements. The above-mentioned plurality of resistor elements have the same resistance value r and the output impedance (or resistance value) of the resistor networks (or resistor elements) connected to all the nodes above is set to a value twice the resistance value r of the above-mentioned resistor elements, or 2r. Accordingly, output impedance at any of the nodes between said plurality of resistor elements represents 2.multidot.r/3.

Abstract: A semiconductor integrated circuit device having an analogue signal processing circuit and a digital signal processing circuit formed on a single semiconductor substrate is disclosed. As an example of the analogue signal processing circuit, a voltage comparator is described. Being liable to be affected by noise, an inverter 2 is formed of an NMOS transistor 41 and a resistance R. For transistor 41 is formed in a well region having a conductivity type (p) opposite to the conductivity type of the substrate (n), it is not easily influenced by noise transmitted through the substrate. Therefore, a voltage comparator independent of the adverse effect of noise from the digital signal processing circuit is obtained.

Abstract: A voltage comparator includes a coupling capacitor which receives at one terminal thereof two signals applied in a complementary fashion, an inverting amplifier having an input coupled to the other terminal of the coupling capacitor and having an output, and switch means coupled between the input and output of the inverting amplifier so as to be in parallel with the inverting amplifier. The duration of an auto-zeroing interval during which the switch means is conductive is maintained constant regardless of the period of the ON-OFF operation of the switch means.

Abstract: In a controlled threshold type electric device having first and second transistors and a differential amplifier which receives a reference input voltage, a voltage corresponding to the threshold voltage of the first transistor itself is applied to the differential amplifier as a feedback input voltage. The differential amplifier compares the received feed back input voltage with the reference input voltage and applies a control voltage to the backgate of the first transistor so that the threshold value of the first transistor converges to a desired value. This control voltage is also applied to the backgate of the second transistor so that the threshold voltage of the second transistor also converges to a desired value. Since the voltage corresponding to the threshold value of the first transistor is applied to the differential amplifier, an accurate feed back control is made. Further, since the differential amplifier can be manufactured through the MOS standard process, the manufacturing cost can be reduced.