Patents by Inventor Shiro Shimizu

Shiro Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9824741
    Abstract: Provided is a refresh control device including: an arbitration operating unit configured to arbitrate (i) a memory access request for accessing a volatile memory that requires a refresh operation for holding data and (ii) a refresh trigger for requesting execution of the refresh operation; and a trigger generating unit configured to generate refresh triggers in a non-constant cycle to satisfy refresh-rate requirements defining the number of refresh operations necessary to be executed per predetermined period for the volatile memory to hold the data.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 21, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGMENT CO., LTD.
    Inventor: Shiro Shimizu
  • Publication number: 20140281201
    Abstract: Provided is a refresh control device including: an arbitration operating unit configured to arbitrate (i) a memory access request for accessing a volatile memory that requires a refresh operation for holding data and (ii) a refresh trigger for requesting execution of the refresh operation; and a trigger generating unit configured to generate refresh triggers in a non-constant cycle to satisfy refresh-rate requirements defining the number of refresh operations necessary to be executed per predetermined period for the volatile memory to hold the data.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: PANASONIC CORPORATION
    Inventor: Shiro SHIMIZU
  • Patent number: 8139453
    Abstract: When receiving the reproduced data from the optical disc and buffering same, the buffering from the correct position can be started on the basis of the synchronous signal and the address information included in the sub data which was received simultaneously. There is provided a method for controlling the buffering of the main data which is reproduced from the optical disc, in which the main data and the sub data are received with taking word clocks which are partitioning timings having plural bits of the main data as a unit as references, a synchronous signal which is in synchronization with the main data is generated, and the buffering of the main data is started on the basis of the synchronous signal.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: March 20, 2012
    Assignee: Panasonic Corporation
    Inventors: Shiro Shimizu, Naoyuki Kashii, Hiroshi Yao, Kiyokatsu Matsui
  • Publication number: 20100226225
    Abstract: The writing in of the reproduced data from the optical disc 101 or the reproduced data from the external USB device 103 into the memory 106 is carried out in such a manner that the data storage formats on the memory 106 of the both writing in are the same storage formats with each other, and the writing in control into the memory 106 and reading out control from the memory 106 are carried out by the similar methods with each other. Thereby, in a data reproduction method having a function of reproducing data which is recorded in the optical disc 101 and a function of reproducing data from an external USB device, a reproduction device which provides no complicated control method as well as gives no large load to the system and is of a high efficiency can be provided.
    Type: Application
    Filed: July 26, 2006
    Publication date: September 9, 2010
    Inventors: Naoyuki Kashii, Shiro Shimizu
  • Publication number: 20100027389
    Abstract: When receiving the reproduced data from the optical disc and buffering same, the buffering from the correct position can be started on the basis of the synchronous signal and the address information included in the sub data which was received simultaneously. There is provided a method for controlling the buffering of the main data which is reproduced from the optical disc, in which the main data and the sub data are received with taking word clocks which are partitioning timings having plural bits of the main data as a unit as references, a synchronous signal which is in synchronization with the main data is generated, and the buffering of the main data is started on the basis of the synchronous signal.
    Type: Application
    Filed: September 7, 2007
    Publication date: February 4, 2010
    Inventors: Shiro Shimizu, Naoyuki Kashii, Hiroshi Yao, Kiyokatsu Matsui
  • Publication number: 20090106624
    Abstract: According to an error correction method of the present invention, in the case of decoding a code word (104) which is doubly encoded by adding first and second inspection data (102,103) having minimum distances d1 and d2 from other data, respectively, a position Ex of an erasure symbol X for which an error was detected using the second inspection data (103) but the error could not be corrected is regarded as an erasure position, and a pseudo erasure symbol Y for which an error was detected using the second inspection data (103) and the error was corrected is regarded as being erroneously corrected and a position Ey of this pseudo erasure symbol is also regarded as an erasure position in first-time decoding, and erasure corrections for up to (d1?d) pieces of symbols are performed at one time using the first inspection data (102) when performing second-time decoding using these position information Ex and Ey.
    Type: Application
    Filed: August 31, 2006
    Publication date: April 23, 2009
    Inventors: Hiroaki Kondo, Shiro Shimizu
  • Patent number: 7013401
    Abstract: The present invention provides a clock control type processor which can permit and accommodate a temporary delay in a processing operation also in a system in which processing times are not constant, and realize the accommodation while reducing the power consumption as much as possible. In this clock control type processor, a block difference detection circuit 20 detects a difference between a processing block address and a writing block address and outputs a block difference signal 105, and a clock control circuit 16 controls a clock.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: March 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shiro Shimizu, Tsuyoshi Takayama, Hiroshi Yasuda
  • Publication number: 20030046600
    Abstract: The present invention provides a clock control type processor which can permit and accommodate a temporary delay in a processing operation also in a system in which processing times are not constant, and realize the accommodation while reducing the power consumption as much as possible. In this clock control type processor, a block difference detection circuit 20 detects a difference between a processing block address and a writing block address and outputs a block difference signal 105, and a clock control circuit 16 controls a clock.
    Type: Application
    Filed: September 5, 2002
    Publication date: March 6, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shiro Shimizu, Tsuyoshi Takayama, Hiroshi Yasuda
  • Patent number: 4958942
    Abstract: An oil seal assembly has an inner annular member and an outer annular member which can rotate relative to each other and are disposed concentrically with each other to have a certain distance from each other in the radial direction. An elastic annular sealing member is bonded to the outer annular member and is in sliding contact with the inner annular member to form sealed annular cavities between the inner and outer annular members. The outer annular member has a cylindrical portion and an annular flange portion. The inner annular member has an inner cylindrical portion, an annular flange portion and an outer cylindrical portion. This outer cylindrical portion is concentric with the inner cylindrical portion to form a certain distance from the inner peripheral surface of the cylindrical portion of the outer annular member. The elastic annular sealing member has a plurality of seal lips which are bonded to the inner peripheral portion of the annular flange portion of the outer annular member.
    Type: Grant
    Filed: September 20, 1989
    Date of Patent: September 25, 1990
    Assignee: Koyo Seiko Co., Ltd.
    Inventor: Shiro Shimizu