Patents by Inventor Shiro Yoshino

Shiro Yoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8573969
    Abstract: A silicon wafer preferable to a semiconductor device is produced by determining a heat treatment condition hardly causing slip dislocations and heat-treating the silicon wafer under the condition. The resistance is calculated by using a calculation formula used for predicting the slip resistance of the wafer from the density, size, and residual solid-solution oxygen concentration of the oxygen precipitation in the silicon wafer, the state of oxygen precipitation such that heat treatment not causing any slip dislocation can be carried out is designed, and thus a silicon wafer heat treatment method under the heat treatment condition not causing any slip dislocation is determined. A silicon wafer heat-treated under such a condition can be provided.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 5, 2013
    Assignee: Sumco TechXIV Corporation
    Inventors: Shinya Sadohara, Kozo Nakamura, Shiro Yoshino
  • Patent number: 8246744
    Abstract: By specifying an initial oxygen concentration in a silicon single crystal and a concentration of thermal donors produced according to a thermal history from 400° C. to 550° C. that the silicon single crystal undergoes during crystal growth, a nucleation rate of oxygen precipitates produced in the silicon single crystal while the silicon single crystal is subjected to a heat treatment is determined. Further, by specifying the heat treatment condition of the silicon single crystal, an oxygen precipitate density and an amount of precipitated oxygen under a given heat treatment condition are predicted by calculation.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: August 21, 2012
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Kozo Nakamura, Junsuke Tomioka, Tetsuro Akagi, Shiro Yoshino
  • Patent number: 7875116
    Abstract: A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystal 6 before annealing. Alternatively, SSD is reduced by polishing after annealing.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: January 25, 2011
    Assignee: Sumco Techxiv Corporation
    Inventors: Shinya Sadohara, Ryota Suewaka, Shiro Yoshino, Kozo Nakamura, Yutaka Shiraishi, Syunji Nonaka
  • Patent number: 7759227
    Abstract: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming a desired internal defect density distribution by controlling a nitrogen concentration distribution in a depth direction of the silicon wafer for heat-treatment, the method including heat-treating a predetermined silicon wafer used for manufacturing a silicon wafer having a denuded zone in the vicinity of the surface thereof.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: July 20, 2010
    Assignee: Sumco Techxiv Corporation
    Inventors: Susumu Maeda, Takahisa Sugiman, Shinya Sadohara, Shiro Yoshino, Kouzo Nakamura
  • Publication number: 20100075267
    Abstract: A silicon wafer preferable to a semiconductor device is produced by determining a heat treatment condition hardly causing slip dislocations and heat-treating the silicon wafer under the condition. The resistance is calculated by using a calculation formula used for predicting the slip resistance of the wafer from the density, size, and residual solid-solution oxygen concentration of the oxygen precipitation in the silicon wafer, the state of oxygen precipitation such that heat treatment not causing any slip dislocation can be carried out is designed, and thus a silicon wafer heat treatment method under the heat treatment condition not causing any slip dislocation is determined. A silicon wafer heat-treated under such a condition can be provided.
    Type: Application
    Filed: September 28, 2007
    Publication date: March 25, 2010
    Inventors: Shinya Sadohara, Kozo Nakamura, Shiro Yoshino
  • Publication number: 20090210166
    Abstract: By specifying an initial oxygen concentration in a silicon single crystal and a concentration of thermal donors produced according to a thermal history from 400° C. to 550° C. that the silicon single crystal undergoes during crystal growth, a nucleation rate of oxygen precipitates produced in the silicon single crystal while the silicon single crystal is subjected to a heat treatment is determined. Further, by specifying the heat treatment condition of the silicon single crystal, an oxygen precipitate density and an amount of precipitated oxygen under a given heat treatment condition are predicted by calculation.
    Type: Application
    Filed: January 27, 2005
    Publication date: August 20, 2009
    Applicant: KOMATSU DENSHI KINZOKU KABUSHIKI KAISHA
    Inventors: Kozo Nakamura, Junsuke Tomioka, Tetsuro Akagi, Shiro Yoshino
  • Publication number: 20090061140
    Abstract: A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystal 6 before annealing. Alternatively, SSD is reduced by polishing after annealing.
    Type: Application
    Filed: February 14, 2006
    Publication date: March 5, 2009
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Shinya Sadohara, Ryota Suewaka, Shiro Yoshino, Kozo Nakamura, Yutaka Shiraishi, Syunji Nonaka
  • Publication number: 20070252239
    Abstract: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming a desired internal defect density distribution by controlling a nitrogen concentration distribution in a depth direction of the silicon wafer for heat-treatment, the method including heat-treating a predetermined silicon wafer used for manufacturing a silicon wafer having a denuded zone in the vicinity of the surface thereof.
    Type: Application
    Filed: April 22, 2005
    Publication date: November 1, 2007
    Applicant: KOMATSU ELECTRONIC METALS CO., LTD.
    Inventors: Susumu Maeda, Takahisa Sugiman, Shinya Sadohara, Shiro Yoshino, Kouzo Nakamura
  • Patent number: 7226505
    Abstract: A method for eliminating defects in single crystal silicon, which comprises subjecting single crystal silicon prepared by the CZ method to an oxidation treatment and then to an ultra high temperature heat treatment at a temperature of at least 1300° C., or comprises subjecting single crystal silicon which is prepared by the CZ method and is not subjected to an oxidation treatment (a bare wafer) to an ultra high temperature heat treatment in an oxygen atmosphere and at a temperature of higher than 1200° C. and lower than 1310° C. The method allows the elimination of void defects present in single crystal silicon with reliability.
    Type: Grant
    Filed: December 25, 2002
    Date of Patent: June 5, 2007
    Assignee: Sumco Techxiv Corporation
    Inventors: Masahiko Ando, Masaru Yuyama, Shiro Yoshino
  • Publication number: 20070113778
    Abstract: A silicon ingot is manufactured by pulling a nitrogen doped silicon single crystal. The oxygen concentration in the crystal is controlled during the pulling, so as to maintain a relationship between the oxygen and nitrogen concentration in the ingot, corresponding to the formula Oi=C1?[C2×(Log Ni)], where C1 and C2 are first and second constants, and Oi is the oxygen concentration and Ni is the nitrogen concentration in the ingot. C1 and C2 will vary depending on the defect criteria. For example, for one criteria C1 may equal to 146.3×1017 and C2 may equal to 9×1017, and Ni may be within the range of approximately 3×1015 to approximately 3×1014 atoms/cm3, while for a stricter defect criteria C1 may equal 127×1017 and C2 may equal 8×1017, and Ni may be within the range proximately 1×1015 to approximately 1×1014 atoms/cm3.
    Type: Application
    Filed: January 16, 2007
    Publication date: May 24, 2007
    Applicant: SUMCO TECHXIV CORPORATION
    Inventors: Satoshi Komiya, Shiro Yoshino, Masayoshi Danbata, Kouchirou Hayashida
  • Publication number: 20050081778
    Abstract: A method for eliminating defects in single crystal silicon, which comprises subjecting single crystal silicon prepared by the CZ method to an oxidation treatment and then to an ultra high temperature heat treatment at a temperature of at least 1300° C., or comprises subjecting single crystal silicon which is prepared by the CZ method and is not subjected to an oxidation treatment (a bare wafer) to an ultra high temperature heat treatment in an oxygen atmosphere and at a temperature of higher than 1200° C. and lower than 1310° C. The method allows the elimination of void defects present in single crystal silicon with reliability.
    Type: Application
    Filed: December 25, 2002
    Publication date: April 21, 2005
    Inventors: Masahiko Ando, Masaru Yuyama, Shiro Yoshino
  • Patent number: 6800132
    Abstract: A method for producing a silicon ingot through pulling up a silicon single crystal according to the Czochralski method, wherein the silicon single crystal is pulled up while being doped with nitrogen in such a condition as to form a part having a nitrogen content of 5×1013 atoms/cm3 to 1×1015 atoms/cm3. A silicon wafer having a nitrogen content of 5×1013 atoms/cm3 to 1×1015 atoms/cm3 which is suitable for being treated with heat in a non-oxidizing atmosphere is manufactured of an ingot produced by using the method. The method can be used for producing a silicon wafer being doped with nitrogen and having satisfactory characteristics for use in a semiconductor device.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: October 5, 2004
    Assignee: Komatsu Denshi Sinzoku Kabushiki
    Inventors: Satoshi Komiya, Shiro Yoshino, Masayoshi Danbata, Kouichirou Hayashida
  • Publication number: 20040065250
    Abstract: An epitaxial silicon wafer which comprises a silicon wafer produced by a method characterized as comprising pulling up a silicon single crystal under a condition wherein when an oxygen concentration is 7×1017 atoms/cm3 a nitrogen concentration is about 3×1015 atoms/cm3 or less, and when an oxygen concentration is 1.6×1018 atoms/cm3 a nitrogen concentration is about 3×1014 atoms/cm3 or less, and, an epitaxial film formed on the wafer. The epitaxial film, being formed on such a wafer, has crystal defects, which are observed as LPD of 120 nm or more on the epitaxial film, in a range of 20 pieces/200-mm wafer or less. The epitaxial silicon wafer contains nitrogen atoms doped therein and also has satisfactory characteristics as that for use in a semiconductor device.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 8, 2004
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Satoshi Komiya, Shiro Yoshino, Masayoshi Danbata, Kouichirou Hayashida
  • Patent number: 5708365
    Abstract: A simple method for evaluating the dielectric breakdown of an oxide layer on a silicon wafer is disclosed. The SPV method is utilized to measure a diffusion length L.sub.on of minority carriers when the silicon wafer is illuminated by white light from another source and a diffusion length L.sub.off of the minority carriers when the silicon wafer is not illuminated by white light from another source. A diffusion length L.sub.safe, which is determined by trap sites in the silicon wafer, is calculated from an equation L.sub.safe =(L.sub.off.sup.-2 -L.sub.on.sup.-2).sup.-1/2. Since L.sub.safe has a strong correlation with the dielectric breakdown of the oxide layer, the dielectric breakdown of the oxide layer can be easily evaluated by L.sub.safe during the fabrication of the silicon wafer.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: January 13, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Shiro Yoshino, Seiichi Shimura, Mitsuo Kono
  • Patent number: 5385115
    Abstract: A semiconductor wafer heat treatment method for improving the yield of devices which are end products by sampling sliced single-crystal silicon wafers made by CZ method to previously calculate the thermal donor concentration of each portion on the wafers and providing them with the IG heat treatment process which causes oxygen precipitation nucleus under the heat treatment condition determined according to the thermal donor concentration so that the change value (delta Oi) of the initial oxygen concentration (initial Oi) before the IG heat treatment to the oxygen concentration after the heat treatment will be kept within a predetermined range.
    Type: Grant
    Filed: May 13, 1993
    Date of Patent: January 31, 1995
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Junsuke Tomioka, Tetsuro Akagi, Shiro Yoshino