Abstract: A clamp auxiliary member is low in manufacturing costs has a simple structure, is applicable to a small-diameter tool, and facilitates replacement of a cutting insert in a cutting tool. The cutting insert is mounted to a tool body by means of the clamp auxiliary member, which is provided with an engagement portion for engaging a fastening screw. The clamp auxiliary member is formed in a ring shape and has one or more slits notching a part thereof. The clamp auxiliary member, and is flexibly deformed at the time the force is applied to an inner peripheral face upper portion thereof from the head portion of the fastening screw to expand the outer diameter. A cutting tool may be provided with such a clamp auxiliary member.

Abstract: A cutting insert has a cutting edge configured to suppress an increase in cutting resistance applied to a cutting boundary portion with an increase in a depth of cut. The cutting insert has a rake face, a flank, and a cutting edge formed at an intersection portion between the rake face and the flank and is removably attachable to a mounting seat. The cutting edge has an angle decreasing portion in which a cutting edge angle gradually decreases in a direction in which the depth of cut of the cutting edge increases. In one embodiment, the rake face includes an upper rake face and a lower rake face. The flank is formed on a side surface between the top and bottom surfaces. The cutting edge is formed at an intersection portion between the upper rake face and the flank.

Abstract: An information processing apparatus comprising a secure information unit that is set to the state not requiring security in the case where the data is transferred from a user memory space to a general purpose register, and that is set to the state requiring security in the case where the data is transferred from a secure memory space to the general purpose register. An encryption key in the secure memory space is prevented from being stolen by prohibiting the data transfer to the user memory space from the general purpose register with the value of the secure information unit set to the state requiring security.

Abstract: An image processing method, comprising registering in advance, to a database, fundamental information and additional information related with the fundamental information, obtaining a first image file, extracting a characteristic information from the first image file, searching a fundamental information of the database which is similar to the characteristic information; and getting a first additional information related with the fundamental information.

Abstract: An information processing apparatus is disclosed, in which the value of a secure information unit is set to the state not requiring security in the case where the data is transferred from a user memory space to a general purpose register, and the value of the secure information unit is set to the state requiring security in the case where the data is transferred from a secure memory space to the general purpose register. An encryption key in the secure memory space is prevented from being stolen by prohibiting the data transfer to the user memory space from the general purpose register with the value of the secure information unit set to the state requiring security.

Abstract: A TLB provided in a memory management apparatus stores an entry for each logical page, and each entry holds an address of a physical page mapped to a corresponding logical page, an index showing the degradation degree of the physical page, and an index showing the access frequency to the logical page. The memory management apparatus accesses a physical page mapped to a desired logical page according to the data stored in the TLB, periodically exchanges the contents between a first physical page mapped to a specific logical page having a largest access frequency index and a second physical page having a smallest degradation index, and then maps the specific logical page to the second physical page. Through the physical page exchange and corresponding mapping process, accesses to each physical page are distributed, so that degradation in storage function is substantially equalized.

Abstract: An inventive information processor performs a predetermined process substantially continuously without causing runaway in its CPU even if extraneous noise has entered the power supply terminal thereof. When the incoming noise reaches relatively low Level 1(L), important information, determining the state of the CPU, is protected by saving it on a register. Thereafter, when the noise level exceeds Level 1(H), important information, representing the status of the predetermined process, is protected by storing it on a memory. Subsequently, when the noise level reaches Level 2, the CPU is suspended. And when the noise has decreased to less than Level 1(L), the predetermined process is resumed in accordance with the information saved and protected on the register and memory. Accordingly, even if noise has entered, the predetermined process can be continued without causing runway in the CPU after having been suspended for a while.

Abstract: An inventive information processor performs a predetermined process substantially continuously without causing runaway in its CPU even if extraneous noise has entered the power supply terminal thereof. When the incoming noise reaches relatively low Level 1(L), important information, determining the state of the CPU, is protected by saving it on a register. Thereafter, when the noise level exceeds Level 1(H), important information, representing the status of the predetermined process, is protected by storing it on a memory. Subsequently, when the noise level reaches Level 2, the CPU is suspended. And when the noise has decreased to less than Level 1(L), the predetermined process is resumed in accordance with the information saved and protected on the register and memory. Accordingly, even if noise has entered, the predetermined process can be continued without causing runway in the CPU after having been suspended for a while.

Abstract: A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time.