Patents by Inventor Shirou Uchiyama

Shirou Uchiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140042617
    Abstract: Disclosed herein is a semiconductor device that includes: a semiconductor substrate including first and second surfaces opposed to each other, a plurality of penetration electrodes each penetrating between the first and second surfaces and a plurality of first metal films each surrounding an associated one of the penetration electrodes with an intervention of an insulating film; and a wiring structure formed on a side of the first surface of the semiconductor substrate, the wiring structure including a plurality of wirings each electrically connected to an associated one of the penetration electrodes.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 13, 2014
    Applicant: Elpida Memory, Inc.
    Inventor: Shirou UCHIYAMA
  • Publication number: 20030054600
    Abstract: A semiconductor memory device is provided, which prevents electrical short-circuit between the conductor lines (e.g., the bit lines) and the contact pads for electrically connecting the lower capacitor electrodes. The first conductive pads are formed to fill the respective contact holes of the first interlayer dielectric film in such a way that the tops of the first pads are lower than the surface of the first interlayer dielectric film. Thus, the gaps are formed on the tops of the first pads in the respective contact holes. The wiring (or conductive) lines, the top faces and side faces of which are covered with the dielectric, are formed on the surface of the first interlayer dielectric film. The wiring lines of the first group are electrically connected to the first conductive pads. The wiring lines of the second group are apart from the respective first conductive pads, thereby electrically insulating the wiring lines of the second group from the first conductive pads.
    Type: Application
    Filed: October 10, 2002
    Publication date: March 20, 2003
    Applicant: NEC Corporation
    Inventor: Shirou Uchiyama
  • Patent number: 6489197
    Abstract: A semiconductor memory device is provided, which prevents electrical short-circuit between the wiring lines (e.g., the bit lines) and the contact pads for electrically connecting the lower capacitor electrodes. The first conauctive pads are formed to fill the respective contact holes of the first interlayer dielectric film in such a way that the tops of the first pads are lower than the surface of the first interlayer dielectric film. Thus, the gaps are formed on the tops of the first pads in the respective contact holes. The wiring (or conductive) lines, the top faces and side faces of which are covered with the dielectric, are formed on the surface of the first interlayer dielectric film. The wiring lines of the first group are electrically connected to the first conductive pads. The wiring lines of the second group are apart from the respective first conductive pads, thereby electrically insulating the wiring lines of the second group from the first conductive pads.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: December 3, 2002
    Assignee: NEC Corporation
    Inventor: Shirou Uchiyama
  • Publication number: 20010041404
    Abstract: A semiconductor memory device is provided, which prevents electrical short-circuit between the wiring lines (e.g., the bit lines) and the contact pads for electrically connecting the lower capacitor electrodes. The first conductive pads are formed to fill the respective contact holes of the first interlayer dielectric film in such a way that the tops of the first pads are lower than the surface of the first interlayer dielectric film. Thus, the gaps are formed on the tops of the first pads in the respective contact holes. The wiring (or conductive) lines, the top faces and side faces of which are covered with the dielectric, are formed on the surface of the first interlayer dielectric film. The wiring lines of the first group are electrically connected to the first conductive pads. The wiring lines of the second group are apart from the respective first conductive pads, thereby electrically insulating the wiring lines of the second group from the first conductive pads.
    Type: Application
    Filed: March 7, 2001
    Publication date: November 15, 2001
    Applicant: NEC Corporation
    Inventor: Shirou Uchiyama