Abstract: Core sampling is enabled over a wide range of areas of the seabed. The present device is provided with a main robot that is moved underwater by remote operation, and a sampling robot that is connected to a manipulator that is attached to the main robot, and that can move in relation to the seabed. The sampling robot is provided with a core tube for excavating the seabed by being rotated and propelled, introducing into the core tube a core of the seabed by the excavation, and breaking the introduced core into core pieces. The main robot is provided with a core rack for storing the core pieces taken from inside the core tube.

Abstract: In order to obtain an optimum depth enhancement effect for three-dimensional (3D) images, a depth information extractor configured to compute depth information from an input video signal, a 2D/3D converter configured to convert, when the input video signal is a two-dimensional (2D) video signal, the 2D video signal to a first video signal which is a 3D video signal based on the depth information, a correction factor calculator configured to compute a correction factor based on the depth information, a selector configured to select either the input video signal or the first video signal and output the selected signal, and a contour enhancement processor configured to perform an enhancement process on the output of the selector based on the correction factor and output the enhanced signal as an output video signal are provided.

Abstract: In order to obtain an optimum depth enhancement effect for three-dimensional (3D) images, a depth information extractor configured to compute depth information from an input video signal, a 2D/3D converter configured to convert, when the input video signal is a two-dimensional (2D) video signal, the 2D video signal to a first video signal which is a 3D video signal based on the depth information, a correction factor calculator configured to compute a correction factor based on the depth information, a selector configured to select either the input video signal or the first video signal and output the selected signal, and a contour enhancement processor configured to perform an enhancement process on the output of the selector based on the correction factor and output the enhanced signal as an output video signal are provided.

Abstract: In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

Abstract: In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

Abstract: A cache memory has a set associative scheme and includes a plurality of ways made up of entries, each entry holding data and a tag; a first holding unit holds, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit, included in a first way among the ways, holds, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit replaces control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein the control unit is further operable to store data into the entry of the way other than the first way.

Abstract: A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

Abstract: In an AV device control, from unit instructions (210, 220, 230) for executing a series of operations, input parts (211, 221, 231) for allowing user inputs to be inputted are respectively extracted and the extracted input parts (211, 221, 231) are concatenated as a first process, and execution parts (212, 222, 232) for operating the AV device according to the inputted user inputs are respectively extracted and the extracted execution parts (212, 222, 232) are concatenated as a second process. Then, the first process is arranged to be followed by the second process to constitute a macro instruction (240). In control using the macro instruction (240), after the user inputs required for executing the macro instruction are all inputted by the first process, the macro instruction by the second process is executed.

Abstract: In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

Abstract: A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of

Abstract: A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of

Abstract: A character string receiving device includes a reception unit for receiving character string data indicating a character string via unidirectional communication, and a character string processing unit for processing the character string data received by the reception unit.

Abstract: A configuration information storage section (108) stores configuration information for allowing a reconfigurable module to execute a predetermined function. A CPU (100) configures attached reconfigurable modules (103 to 106) according to the number thereof by referencing the configuration information stored in the configuration information storage section (108).

Abstract: A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of

Abstract: A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of

Abstract: A TLB provided in a memory management apparatus stores an entry for each logical page, and each entry holds an address of a physical page mapped to a corresponding logical page, an index showing the degradation degree of the physical page, and an index showing the access frequency to the logical page. The memory management apparatus accesses a physical page mapped to a desired logical page according to the data stored in the TLB, periodically exchanges the contents between a first physical page mapped to a specific logical page having a largest access frequency index and a second physical page having a smallest degradation index, and then maps the specific logical page to the second physical page. Through the physical page exchange and corresponding mapping process, accesses to each physical page are distributed, so that degradation in storage function is substantially equalized.

Abstract: A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

Abstract: A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

Abstract: A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits the distribution request to a program distribution device and transmits the device information to an inspection device. The program distribution device transmits the program in the distribution request to the inspection device. The inspection device inspects a materialization state of the information contents in the terminal device based on the program and the device information and transmits a result of the inspection to the program distribution device and the contents distribution device.

Abstract: A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of