Abstract: A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scale-up type by making SMP coupling among nodes. Each node has a unit for SMP coupling to other nodes. A module management unit responds to system configuration information to switch between a mode in which the node operates singularly as a braid server and a mode in which the node operates as a constituent module of an SMP server. Links among individual nodes are laid through equidistant wiring lines on a back plane and additionally a loop wiring line having a length equal to that of the inter-node link on the back plane is also laid in each node, thereby setting up synchronization among the nodes. Synchronization of reference clocks for SMP coupled nodes is also established.

Abstract: A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scale-up type by making SMP coupling among nodes. Each node has a unit for SMP coupling to other nodes. A module management unit responds to system configuration information to switch between a mode in which the node operates singularly as a braid server and a mode in which the node operates as a constituent module of an SMP server. Links among individual nodes are laid through equidistant wiring lines on a back plane and additionally a loop wiring line having a length equal to that of the inter-node link on the back plane is also laid in each node, thereby setting up synchronization among the nodes. Synchronization of reference clocks for SMP coupled nodes is also established.

Abstract: An interserver communication mechanism which can eliminate the need for preparing an external I/O device for each of physical servers for communication between the physical servers and can avoid generation of overhead caused by protocol conversion. A plurality of physical servers are connected to the interserver communication mechanism via I/O link and I/O switch. The interserver communication mechanism has a read instruction generator for issuing an instruction to access data of the physical servers and a write instruction generator for transmitting the read data to the other server. Data transfer between the physical servers is carried out in the interior of the interserver communication mechanism by reading out data from a data transmission originator, writing the read data to a transmission destination as it is, and directly turning back the data at the interserver communication mechanism.

Abstract: In a shared memory multiprocessor system, data reading accesses and data write-back completion notifications are selected in synchronism with all of the nodes to order them. In each of the nodes, a subject address of ordered data reading access is compared with a subject address of ordered data write-back completion notification to detect a data reading operation of the same address which is passed by the completion of the data writing-back operation. Both a data reading sequence and a data writing-back sequence are determined. At this time, such a coherency response for prompting a re-reading operation of the data is transmitted to the node which transmitted the data reading access, so that coherency of the data is maintained.

Abstract: In a shared memory multiprocessor system, data reading accesses and data write-back completion notifications are selected in synchronism with all of the nodes to order them. In each of the nodes, a subject address of ordered data reading access is compared with a subject address of ordered data write-back completion notification to detect a data reading operation of the same address which is passed by the completion of the data writing-back operation. Both a data reading sequence and a data writing-back sequence are determined. At this time, such a coherency response for prompting a re-reading operation of the data is transmitted to the node which transmitted the data reading access, so that coherency of the data is maintained.

Abstract: A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scaleup type by making SMP coupling among nodes. Each node has a unit for SMP coupling to other nodes and a module management unit of each node responds to system configuration information to switch between mode in which the node operates singularly as a braid server and mode in which the node operates as a constituent module of an SMP server. Links among individual nodes are laid through equidistant wiring lines on a back plane and besides a loop wiring line having length equal to that of the inter-node link on back plane is also laid in each node, thereby setting up synchronization among nodes. Each node has a reference clock distribution unit mounted on back plane and adapted to distribute reference clocks to individual nodes and by switching reference clocks by a clock distributor inside each node, synchronization of reference clocks for SMP coupled nodes can be established.

Abstract: Destination registers are provided in a chipset and node information is set in the destination registers. The destination address is selected in accordance with a physical address to be accessed to thereby decided a node provided with a memory to be accessed. The magnitude of the load of the memory access to the node can be changed in accordance with setting of the node information in the destination registers. Optimum node information can be set in the destination registers in accordance with the number of nodes increased and the transfer speed and the capacity of the memory to thereby increase the flexibility and uniform the throughput of memory access to each node.

Abstract: In a bus or switch coupled system having a plurality of processor modules and a memory module, the memory module is provided with a unit for returning a write completion acknowledgement (WRITE_ACK) to a write requesting processor module. If a processor module PM1 is under execution of write-back of a cache line upon arrival of a cache coherence check (CCC) issued from a processor module with a cache miss of the cache line, an “INVALID” signal is returned to the CCC issued processor module PMO after a write completion acknowledgment from the memory module is confirmed and the cache line is invalidated. After confirming the “INVALID” signals from other processor modules, the CCC issued processor module issues a READ transaction to the memory module to obtain correct latest data reflecting the write-back data of the processor module.

Abstract: In a cache coherency control method of a multi-processor system comprising a plurality of cache systems of identical configuration-after "method", for quickly determining consistency of a data block designated by a cache coherency request issued by other cache system a multi-processor system using the same, systems have identical configuration and each of the cache systems includes a history table for storing an address included in an access request flowing over a shared bus and a history table control circuit. The history table control circuit determines whether an address of a received access request is stored in the history table, and when the address is stored in the history table, suppresses the operation of a cache control circuit for the access request, and alternatively when the address is not stored in the address table, conducts the operation of the cache control circuit for the access request.