Abstract: A base substrate and a first metal layer laminated on the base substrate are included. A first laminated portion and a second laminated portion are arranged on and directly contact a side of the first metal layer. The first laminated portion includes a first insulating layer, a second metal layer, a second insulating layer and a first conductive layer. The first laminated portion is arranged with a first via. The second laminated portion includes a third insulating layer and a second conductive layer laminated on the third insulating layer. The second laminated portion is arranged with a second via. The first via is connected to the first conductive layer, the second via is connected to the second conductive layer, and the first conductive layer is connected to the second conductive layer. The second laminated portion is extended to reach an edge of the first metal layer.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a display area and a non-display area in which a peripheral circuit is provided. The peripheral circuit includes a test area, a bonding area, and a cutting area. The test area is provided with a test signal line for providing a test signal. The bonding area is adjacent to the display area, and the bonding area and the test area are electrically connected through signal leads. The cutting area is disposed between the test area and the bonding area. After a cutting process is completed in the cutting area, a cutting opening is formed on each signal lead. A position of the cutting opening of at least one signal lead is different from positions of the cutting openings of other signal leads in height along an extending direction of the signal leads.

Abstract: Provided is an array substrate, a manufacturing method for an array substrate, and a display panel. The array substrate includes a first substrate base, common electrode lines, a color filter layer, and a planarization layer; the color filter layer includes first color filters and a second color filters, forming color filter channels therebetween on the common electrode lines, so as to avoid overlapping between the first color filters and the second color filters. The width of the common electrode lines is relatively small, ensuring a high aperture rate of the array substrate. Additionally, the array substrate further includes a planarization layer filled in the color filter channels, this minimizes the color filter channels to ensure flatness between the first color filters and the second color filters, so that etching residues in the color filter channels can be avoided when forming the pixel electrode layer.

Abstract: The shorting bar includes a test signal wiring layer, an insulating layer, a signal lead layer, a protective layer and a bonding lead layer that are sequentially stacked. The test signal wiring layer is arranged with test signal lines, and the signal lead layer is arranged with signal leads. The test signal lines are made of a transparent conductive material, and a coverage region of the insulating layer and a coverage region of the protective layer are staggered from coverage regions of the test signal lines; or, the signal leads are made of the transparent conductive material, the coverage region of the protective layer is staggered from coverage regions of the signal leads; or, the protective layer is arranged with a plurality of first through holes, and the first through holes correspond to the signal leads in a one-to-one correspondence.

Abstract: The embodiments relate to array substrate technologies. Provided is an array substrate and a display panel, the array substrate includes a display region and a non-display region. A first bonding-lead part, a second bonding-lead part and a third bonding-lead part are arranged in sequence in a bonding area of the non-display region. A first side of the first bonding-lead part is used for connecting with a gate driver unit test wiring, and a second side of the first bonding-lead part is used for connecting with a gate driver signal wiring. A width of the first bonding-lead part is smaller than that of the second bonding-lead part, such that a wiring area is formed on the first side of the first bonding-lead part and/or the second side of the first bonding-lead part, thereby providing sufficient wiring space for the GOA unit test wiring and the GOA signal wiring.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a display area and a non-display area in which a peripheral circuit is provided. The peripheral circuit includes a test area, a bonding area, and a cutting area. The test area is provided with a test signal line for providing a test signal. The bonding area is adjacent to the display area, and the bonding area and the test area are electrically connected through signal leads. The cutting area is disposed between the test area and the bonding area. After a cutting process is completed in the cutting area, a cutting opening is formed on each signal lead. A position of the cutting opening of at least one signal lead is different from positions of the cutting openings of other signal leads in height along an extending direction of the signal leads.

Abstract: The present application discloses a cutting method for a display panel, a display panel and a display device, the cutting method for a display panel including a cutting stage of a side edge of a binding area and a cutting stage of a side edge of a non-binding area, the cutting stage of a side edge of a non-binding area includes steps of: aligning a cutter according to an alignment mark preset on the side edge of the non-binding area on the display panel, so that a cutter on a second substrate side is closer to a display area of the display panel than a cutter on a first substrate side, and cutting the first substrate and the second substrate by the cutter on the second substrate side and the cutter on the first substrate side respectively.

Abstract: A base substrate and a first metal layer laminated on the base substrate are included. A first laminated portion and a second laminated portion are arranged on and directly contact a side of the first metal layer. The first laminated portion includes a first insulating layer, a second metal layer, a second insulating layer and a first conductive layer. The first laminated portion is arranged with a first via. The second laminated portion includes a third insulating layer and a second conductive layer laminated on the third insulating layer. The second laminated portion is arranged with a second via. The first via is connected to the first conductive layer, the second via is connected to the second conductive layer, and the first conductive layer is connected to the second conductive layer. The second laminated portion is extended to reach an edge of the first metal layer.

Abstract: Provided is an array substrate, a manufacturing method for an array substrate, and a display panel. The array substrate includes a fist substrate base, common electrode lines, a color filter layer, and a planarization layer; the color filter layer includes first color filters and a second color filters, forming color filter channels therebetween on the common electrode lines, so as to avoid overlapping between the first color filters and the second color filters. The width of the common electrode lines is relatively small, ensuring a high aperture rate of the array substrate. Additionally, the array substrate further includes a planarization layer filled in the color filter channels, this minimizes the color filter channels to ensure flatness between the first color filters and the second color filters, so that etching residues in the color filter channels can be avoided when forming the pixel electrode layer.

Abstract: The embodiments relate to array substrate technologies. Provided is an array substrate and a display panel, the array substrate includes a display region and a non-display region. A first bonding-lead part, a second bonding-lead part and a third bonding-lead part are arranged in sequence in a bonding area of the non-display region. A first side of the first bonding-lead part is used for connecting with a gate driver unit test wiring, and a second side of the first bonding-lead part is used for connecting with a gate driver signal wiring. A width of the first bonding-lead part is smaller than that of the second bonding-lead part, such that a wiring area is formed on the first side of the first bonding-lead part and/or the second side of the first bonding-lead part, thereby providing sufficient wiring space for the GOA unit test wiring and the GOA signal wiring.

Abstract: The present application discloses a cutting method for a display panel, a display panel and a display device, the cutting method for a display panel including a cutting stage of a side edge of a binding area and a cutting stage of a side edge of a non-binding area, the cutting stage of a side edge of a non-binding area includes steps of: aligning a cutter according to an alignment mark preset on the side edge of the non-binding area on the display panel, so that a cutter on a second substrate side is closer to a display area of the display panel than a cutter on a first substrate side, and cutting the first substrate and the second substrate by the cutter on the second substrate side and the cutter on the first substrate side respectively.

Abstract: A liquid crystal display panel and a display device, where the liquid crystal display panel includes a color film substrate and an array substrate, the color film substrate includes a first base substrate and a first electrode layer arranged on the first base substrate, the array substrate includes a second base substrate and a second electrode layer arranged on the second base substrate, a distance between the second electrode layer and the first electrode layer is greater than or equal to a threshold value; the threshold value is a critical safety distance that causes a generation of arc discharge between the first electrode layer and the second electrode layer. According to the embodiments, a problem that the existing liquid crystal display panel has a weak anti-static-electricity ability, so that electrodes of the liquid crystal display panel are prone to be damaged is solved.

Abstract: The present application discloses a display panel, a display device, and a manufacturing method. The display panel includes a plurality of first pixels and a plurality of second pixels, where a color of each first pixel is different from that of each second pixel; the first pixels are configured as a high domain region, and the second pixels are configured as a low domain region; the number of alignment regions of the high domain region is greater than that of alignment regions of the low domain region; and the lightness of the first pixels is higher than that of the second pixels.

Abstract: This application discloses a display panel and a display device. The display panel (101) includes a first substrate (110), which includes a plurality of pixels (111). Each of the pixels (111) includes a plurality of sub-pixels of different colors. The sub-pixels of each color include a first sub-pixel (122) and a second sub-pixel (123). The aperture ratio of the first sub-pixel (122) is smaller than the aperture ratio of the second sub-pixel (123).

Abstract: A method for manufacturing a cross-line structure includes the steps of etching to obtain a first conductive layer, depositing a second conductive material and a photoresist material on the first conductive layer, and removing the part of the photoresist material on a position where a second conductive layer is not required by means of a photomask. The method further includes the steps of etching the second conductive material, obtaining the second conductive layer, and performing compensation on a photomask graphic so that the width of an overlap portion of the second conductive layer with the first conductive layer is greater than or equal to the width of the portion of the second conductive layer that does not overlap the first conductive layer.

Abstract: The present application discloses a display panel, a display device, and a manufacturing method. The display panel includes a plurality of first pixels and a plurality of second pixels, where a color of each first pixel is different from that of each second pixel; the first pixels are configured as a high domain region, and the second pixels are configured as a low domain region; the number of alignment regions of the high domain region is greater than that of alignment regions of the low domain region; and in the display panel, the number of alignment regions of the pixels of the same row or the same column is the same.

Abstract: This application discloses a display panel, a display device, and a manufacturing method. The display panel includes: a plurality of first pixels and a plurality of second pixels, where colors of the first pixel differ from colors of the second pixel; and the first pixel is configured to be a high domain, the second pixel is configured to be a low domain, and the number of alignment regions of the high domain is greater than the number of alignment regions of the low domain.

Abstract: A display panel comprises: an array substrate on which common wiring is provided; a color filter substrate cell-assembled with the array substrate, a common electrode corresponding to the common wiring being provided on the color filter substrate; a sealant disposed between the array and filter substrates, and enclosing a liquid crystal accommodating space with the array and filter substrates; and a conductive glue ball embedded in the sealant and used for conducting the wiring of the array substrate and the electrode of the filter substrate. The non-display region of the array substrate comprises a transfer region corresponding to the position of the glue ball and a surrounding region disposed around the transfer region; taking the surface of the array substrate distant from the filter substrate as a reference, the height of the surrounding region of the array substrate is less than the maximum height of the transfer region of the array substrate.

Abstract: The present application discloses a cutting method for a display panel, a display panel and a display device, the cutting method for a display panel including a cutting stage of a side edge of a binding area and a cutting stage of a side edge of a non-binding area, the cutting stage of a side edge of a non-binding area includes steps of: aligning a cutter according to an alignment mark preset on the side edge of the non-binding area on the display panel, so that a cutter on a second substrate side is closer to a display area of the display panel than a cutter on a first substrate side, and cutting the first substrate and the second substrate by the cutter on the second substrate side and the cutter on the first substrate side respectively.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a display area and a non-display area in which a peripheral circuit is provided. The peripheral circuit includes a test area, a bonding area, and a cutting area. The test area is provided with a test signal line for providing a test signal. The bonding area is adjacent to the display area, and the bonding area and the test area are electrically connected through signal leads. The cutting area is disposed between the test area and the bonding area. After a cutting process is completed in the cutting area, a cutting opening is formed on each signal lead. A position of the cutting opening of at least one signal lead is different from positions of the cutting openings of other signal leads in height along an extending direction of the signal leads.