Abstract: A semiconductor integrated circuit has a function circuit, which is composed of flip-flop (F/F) groups 1 and 1 formed by a plurality of flip-flops, a combinational circuit 3 arranged between the F/F groups 1 and 2 and formed by a plurality of paths including various logical gates, a dual input logical gate 5, an output buffer 6 and an input buffer 7. In the combinational circuit 3, there are a plurality of paths, which stretch from the output side of the F/F group 1 to the input side of the F/F group 2. However, only a critical path 20 having a largest delay time is shown. For the plurality of logical gates included in the critical path 20, only an initial stage logical gate 4 is shown and all of the logical gates which are cascade connected thereafter are omitted. Thus, a semiconductor integrated circuit and its evaluating method for easily and inexpensively performing AC testing are provided without increasing a chip size.

Abstract: In a semiconductor device including a logic gate combination circuit and a plurality of scan registers or flip-flops, a scan path is provided to serially connect the flip-flops to each other. Scan clock signals are sequentially generated and transmitted to the scan registers. A delay time among the scan clock signals is approximately smaller than an operation time of each of the scan registers.

Abstract: For reduction in occupation area, there is provided a programmable logic array circuit fabricated on a seminconductor substrate comprising (a) a plurality of true signal lines arranged in rows, (b) a plurality of complementary signal lines each intervening between adjacent two of the true signal lines, (c) a plurality of product term lines arranged in columns, (d) a first source of constant voltage supplying a first constant voltage level to the product term lines, (e) a second source of constant voltage producing a second constant voltage level different from the first constant voltage level, and (f) a plurality of active device areas each located under that area defined by one of the true signal lines, one of the complementary signal lines adjacent to aforesaid one of the true signal lines and adjacent two of the product term lines, and each of the active device area has two field effect transistors gate electrodes of which can be connected to either of the true signal line and the complementary signal line