Abstract: An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.

Abstract: A trench structure and fabrication technique is disclosed for isolating adjacent circuits in an integrated circuit. A trench (26) is coated with an oxidation barrier (18) of silicon to protect underlying semiconductor regions (34, 36) from crystal faults and dislocations caused by high temperature oxidation. The trench (26) includes a bottom (50) formed of the substrate (10). The trench (26) is filled with a conductive material which is in electrical contact with the substrate (10). A top surface contact electrode (74) is formed over the trench, in contact therewith, thereby also contacting the underlying substrate (10). For very narrow trenches, semiconductor areas (68, 70) are formed adjacent the top of the trench to thereby provide additional contact surface for the electrode (74).