Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.

Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.

Abstract: A non-volatile (NV) memory write method using data protection with aid of pre-calculation information rotation, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory write method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through pre-calculation information rotation type encoding, wherein regarding a message: starting encoding a message to calculate a partial parity code according to the message and a transpose matrix of a part-one matrix within a parity check matrix; loading a partial matrix of an inverse matrix of a part-two matrix within the parity check matrix from a storage circuit; applying the partial matrix and its rotated version(s) generated through rotation control to generate and output a corresponding parity code; and writing into the NV memory.

Abstract: An encoder of a flash memory controller is provided, which includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. The barrel shifter module processes multiple data blocks to generate multiple partial parity blocks including a first portion, a second portion and a third portion. The inverse matrix calculating circuit performs inverse matrix calculating operations on the first portion to generate a first portion of parity blocks. The calculating circuit performs inverse matrix calculating operations on the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity blocks. The first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity blocks serve as multiple parity blocks generated in response to encoding the data blocks.

Abstract: The present invention provides an encoding circuit of a flash memory controller, wherein the encoding circuit includes an auxiliary data generating circuit and an encoder. In the operations of the encoding circuit, the auxiliary data generating circuit is configured to receive a plurality of data chunks to generate auxiliary data corresponding to the data chunks. The encoder is configured to encode the data blocks to generate parity codes according to a parity check matrix, and to use the auxiliary data to replace a portion of the parity codes to generate adjusted parity codes, wherein the data chunks and the adjusted parity codes are written into a flash.

Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.

Abstract: An encoder of a flash memory controller is provided, which includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. The barrel shifter module processes multiple data blocks to generate multiple partial parity blocks including a first portion, a second portion and a third portion. The inverse matrix calculating circuit performs inverse matrix calculating operations on the first portion to generate a first portion of parity blocks. The calculating circuit performs inverse matrix calculating operations on the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity blocks. The first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity blocks serve as multiple parity blocks generated in response to encoding the data blocks.

Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.

Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.

Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.

Abstract: An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.

Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.