Abstract: A pixel array includes many scan lines, data lines and pixel structures coupled to the scan lines and data lines. Each of the pixel structures includes a first pixel unit and a second pixel unit. Each of the first pixel units includes a first switch device. Each of the second pixel units includes a second switch device and a coupling capacitor. In each of the pixel structures in an ith row, a control end and a first end of the first switch device are respectively coupled to the ith scan line and one of the data lines; a control end and a first end of the second switch device are respectively coupled to the (i?1)th scan line and a second end of the first switch device. The coupling capacitor is coupled between the second end of the first switch device and a second end of the second switch device.

Abstract: A thin film transistor array substrate includes a substrate having a plurality of pixel units arranged in a matrix, a plurality of first gate lines and second gate lines alternately arranged on the substrate, a plurality of source lines perpendicular to the first gate lines and the second gate lines formed on the substrate, and a plurality of thin film transistors respectively positioned in the pixel units. Each of the source lines further includes a main source line and a sub source line electrically connected to each other in parallel connection.

Abstract: A pixel array includes many scan lines, data lines and pixel structures coupled to the scan lines and data lines. Each of the pixel structures includes a first pixel unit and a second pixel unit. Each of the first pixel units includes a first switch device. Each of the second pixel units includes a second switch device and a coupling capacitor. In each of the pixel structures in an ith row, a control end and a first end of the first switch device are respectively coupled to the ith scan line and one of the data lines; a control end and a first end of the second switch device are respectively coupled to the (i?1)th scan line and a second end of the first switch device. The coupling capacitor is coupled between the second end of the first switch device and a second end of the second switch device.

Abstract: A pixel structure including a substrate, a scan line, a patterned common line, an active device, a data line, a passivation layer, and a pixel electrode is provided. The scan line, the patterned common line, and the active device are disposed on the substrate. The active device has an insulation layer extending outward to cover the scan line and the patterned common line. Besides, the patterned common line has at least a first side and a second side. Extending directions of the first side and the second side together form a first included angle. The data line is disposed on the insulation layer, and the active device is electrically connected to the scan line and the data line. The passivation layer covers the active device. The pixel electrode is disposed on the passivation layer and electrically connected to the active device.

Abstract: A pixel structure including a substrate, a scan line, a patterned common line, an active device, a data line, a passivation layer, and a pixel electrode is provided. The scan line, the patterned common line, and the active device are disposed on the substrate. The active device has an insulation layer extending outward to cover the scan line and the patterned common line. Besides, the patterned common line has at least a first side and a second side. Extending directions of the first side and the second side together form a first included angle. The data line is disposed on the insulation layer, and the active device is electrically connected to the scan line and the data line. The passivation layer covers the active device. The pixel electrode is disposed on the passivation layer and electrically connected to the active device.