Abstract: A frequency stabilizing device of an oscillator is disclosed. The frequency stabilizing device of an oscillator is used for stabilizing the frequency of an oscillator to keep the frequency in constant when input voltage is changed. The frequency stabilizing device comprises a plurality of transmission gates for receiving an input voltage and generating a current and a plurality of resistors for control the value of the current, wherein the current is positive in relation to the input voltage and the frequency of the oscillator is determined by the current.

Abstract: A power source circuit for an oscillator is provided comprising a multiplexer, a plurality of transmission gates, a plurality of resistors, a current source circuit, and an output circuit. The multiplexer inputs a digital signal and outputs one or more control signals. The transmission gates is individually coupled to the multiplexer and receives the one or more control signals, wherein each of the plurality of transmission gates are turned on or off according to the one or more control signals. The plurality of resistors is coupled in series and individually coupled to the plurality of transmission gates. The current source circuit is coupled to the plurality of resistors and provides a current source. The output circuit is coupled to the current source and provides output power for the oscillator according to the current source and the operation of the transmission gates.

Abstract: A stabilizing current source circuit is provided. The stabilizing current source circuit is used for stabilizing a current provided by a current source, and the current of the current source increases when temperature rises. The stabilizing current source circuit comprises a current source circuit and an adjustment circuit. The current source circuit provides a current that increases when temperature rises. The adjustment circuit is coupled to the current source circuit and provides an input current that increases when temperature rises. The current of the current source is subtracted from the input current to generate a current source current which does not vary with temperature.

Abstract: A stabilizing method for a current source is provided. The current source is provided a current which increases when temperature rises. An adjustment circuit provides an input current increasing when temperature rises. A rising ratio of the input current with temperature is the same as a rising ratio of the current of the current source with temperature. The current of the current source is subtracted from the input current. After the current of the current source is subtracted from the input current, the current of the current source does not vary when temperature varies.

Abstract: An output driving circuit is disclosed, providing an output signal at an output node and comprises an inverter and an output driver. A first P-type transistor and a first N-type transistor of the inverter are coupled in series between high and low voltage sources and controlled respectively by first and second driving signals. A gate oxide layer of the first N-type transistor is thinner than that of the first P-type transistor. The inverter generates a first driving signal. A second P-type transistor and a second N-type transistor of the output driver are coupled in series at the output node between the high and low voltage sources. The second P-type transistor and the second N-type transistor are controlled respectively by the first driving signal and a second driving signal. A falling time of the first driving signal is longer than a falling time of the second driving signal.

Abstract: An output driving circuit is disclosed, providing an output signal at an output node and comprises an inverter and an output driver. A first P-type transistor and a first N-type transistor of the inverter are coupled in series between high and low voltage sources and controlled respectively by first and second driving signals. A gate oxide layer of the first N-type transistor is thinner than that of the first P-type transistor. The inverter generates a first driving signal. A second P-type transistor and a second N-type transistor of the output driver are coupled in series at the output node between the high and low voltage sources. The second P-type transistor and the second N-type transistor are controlled respectively by the first driving signal and a second driving signal. A falling time of the first driving signal is longer than a falling time of the second driving signal.

Abstract: An oscillator voltage source circuit is provided comprising a multiplexer, a plurality of transmission gates, a plurality of resistors, a voltage source circuit, and an output circuit. The multiplexer inputs a digital signal. The transmission gates is individually coupled to the multiplexer and receives the digital signal, wherein the plurality of transmission gate are turned on or off according to the digital signal. The plurality of resistors is coupled in series and individually coupled to the plurality of transmission gates. The voltage source circuit is coupled to the plurality of resistors and provides a first voltage source. The output circuit is coupled to the voltage source and outputs an oscillator voltage source according to the first voltage source and the turned-on or turned-off transmission gates.

Abstract: A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.

Abstract: A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the controllable delay circuits is coupled to the phase detecting unit, the phase detecting unit samples a positive received signal at the transition points of a specific period signal transmitted by each of the controllable delay circuits.

Abstract: A frequency stabilizing device of an oscillator is disclosed. The frequency stabilizing device of an oscillator is used for stabilizing the frequency of an oscillator to keep the frequency in constant when input voltage is changed. The frequency stabilizing device comprises a plurality of transmission gates for receiving an input voltage and generating a current and a plurality of resistors for control the value of the current, wherein the current is positive in relation to the input voltage and the frequency of the oscillator is determined by the current.

Abstract: A stabilizing method for a current source is provided. The current source is provided a current which increases when temperature rises. An adjustment circuit provides an input current increasing when temperature rises. A rising ratio of the input current with temperature is the same as a rising ratio of the current of the current source with temperature. The current of the current source is subtracted from the input current. After the current of the current source is subtracted from the input current, the current of the current source does not vary when temperature varies.

Abstract: A stabilizing current source circuit is provided. The stabilizing current source circuit is used for stabilizing a current provided by a current source, and the current of the current source increases when temperature rises. The stabilizing current source circuit comprises a current source circuit and an adjustment circuit. The current source circuit provides a current that increases when temperature rises. The adjustment circuit is coupled to the current source circuit and provides an input current that increases when temperature rises. The current of the current source is subtracted from the input current to generate a current source current which does not vary with temperature.

Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

Abstract: A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.

Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

Abstract: A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the controllable delay circuits is coupled to the phase detecting unit, the phase detecting unit samples a positive received signal at the transition points of a specific period signal transmitted by each of the controllable delay circuits.