Patents by Inventor Shiv Harit Mathur

Shiv Harit Mathur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12191854
    Abstract: Systems and methods for improving the power, performance, and area (PPA) for a voltage mode driver and on die termination (ODT). A voltage mode driver having first and second circuits in a pulldown design. The first circuit has a plurality of nMOS devices in parallel, the plurality of nMOS devices being common to a first resistor. The second circuit is in parallel with the first circuit and has an nMOS device in series with a second resistor. The second circuit is configured to be enabled when the pulldown impedance of the first circuit, with the second circuit disabled and all of the nMOS devices of the first circuit turned on, is greater than a desired pulldown impedance. The voltage mode driver may also be a pullup design, or have both pulldown and pullup stages.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: January 7, 2025
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Nirav Natwarbhai Patel, Shiv Harit Mathur, Sai Ravi Teja Konakalla
  • Publication number: 20240403243
    Abstract: Embodiments of the disclosed technology relate to the operation of devices including memory devices, and more particularly to valid window maximization in a toggle mode (TM) or Open NAND Flash Interface (ONFI) link using systematic skew while compensating for simultaneous switching outputs (SSO) and cross talk.
    Type: Application
    Filed: July 27, 2023
    Publication date: December 5, 2024
    Inventors: SHIV HARIT MATHUR, NIRAVKUMAR NATWARBHAI PATEL
  • Publication number: 20240379138
    Abstract: An apparatus is provided that includes a first pull-up driver circuit coupled to a first calibration node, an internal resistor circuit and first input/output pad on an integrated circuit die, a second pull-up driver circuit coupled to a second calibration node and second input/output pad on the integrated circuit die, a third pull-up driver circuit coupled to a third calibration node, a comparator including a first input terminal selectively coupled to the first calibration node, the second calibration node and the third calibration node, and a second input terminal coupled to a reference voltage, and circuitry configured to trim the reference voltage to compensate for a comparator offset, and trim an impedance of the internal resistor circuit by comparing a voltage on the first calibration node and the trimmed reference voltage. The trimmed impedance of the internal resistor circuit substantially equals a desired impedance of the third pull-up driver circuit.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 14, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventor: Shiv Harit Mathur
  • Publication number: 20240347120
    Abstract: Embodiments of the present technology provide memory cards intelligently designed to provide protection when mistakenly inserted into non-memory card hosts. Embodiments achieve such protection with less footprint/circuitry than existing fail-safe solutions, and without electrical overstress-causing offset voltages characteristic of existing fail-safe solutions. To realize these advantages, a memory card of the present technology includes a fail-safe reference voltage supply circuit that operates in a “fail-safe mode” by default, and exits and re-enters the fail-safe mode in response to voltage mode driver output enable (OE) signals.
    Type: Application
    Filed: July 31, 2023
    Publication date: October 17, 2024
    Inventors: SHIV HARIT MATHUR, Sai Ravi Teja KONAKALLA, Niravkumar Natwarbhai PATEL, Utkarsh SRIVASTAVA, Gopikrishna SIDDULA
  • Publication number: 20240304615
    Abstract: Embodiments of the present technology provide transceivers intelligently designed to reduce voltage kickback and I/O pad capacitance. A transceiver of the present technology can reduce voltage kickback by dynamically tracking I/O pad voltage at gate terminals of reference voltage signal-receiving MOS devices of a voltage mode cascoded driver implemented in the transceiver. By tracking I/O pad voltage, embodiments can reduce/avoid rapidly changing voltage differentials across the reference voltage signal-receiving MOS devices-thereby reducing voltage kickback. By reducing voltage kickback, embodiments can maintain reliability and improve performance for the transceiver. Tracking I/O pad voltage at the gate terminals of the reference voltage signal-receiving MOS devices can also reduce I/O pad capacitance of the transceiver-thereby improving performance for the transceiver.
    Type: Application
    Filed: July 31, 2023
    Publication date: September 12, 2024
    Inventors: SHIV HARIT MATHUR, SAI RAVI TEJA KONAKALLA, NIRAVKUMAR NATWARBHAI PATEL, UTKARSH SRIVASTAVA, GOPIKRISHNA SIDDULA
  • Publication number: 20240220134
    Abstract: The application discloses a system for altering an input/output (I/O) data signal of a NAND programming operation. The system includes a skew-gen circuit comprising: a delay block coupled to an input of a two input logic OR gate, and a MUX logic gate coupled to an output of the logic OR gate. The skew-gen circuit is configured to: alter the pulse width of a input data signal by increasing the width of the data high signal and decreasing the width of the data low signal; and output the altered data signal to the MUX, the MUX configured to select either the altered data signal or the input data signal depending on the mode.
    Type: Application
    Filed: July 18, 2023
    Publication date: July 4, 2024
    Inventors: NIRAVKUMAR NATWARBHAI PATEL, SHIV HARIT MATHUR, SUMANTH REDDY RATHNA
  • Patent number: 11984168
    Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: May 14, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Nitin Gupta, Shiv Harit Mathur, Ramakrishnan Subramanian, Dmitry Vaysman
  • Publication number: 20240097681
    Abstract: Systems and methods for improving the power, performance, and area (PPA) for a voltage mode driver and on die termination (ODT). A voltage mode driver having first and second circuits in a pulldown design. The first circuit has a plurality of nMOS devices in parallel, the plurality of nMOS devices being common to a first resistor. The second circuit is in parallel with the first circuit and has an nMOS device in series with a second resistor. The second circuit is configured to be enabled when the pulldown impedance of the first circuit, with the second circuit disabled and all of the nMOS devices of the first circuit turned on, is greater than a desired pulldown impedance. The voltage mode driver may also be a pullup design, or have both pulldown and pullup stages.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: NIRAV NATWARBHAI PATEL, SHIV HARIT MATHUR, SAI RAVI TEJA KONAKALLA
  • Publication number: 20240072804
    Abstract: Improved voltage level shifters are disclosed capable of achieving substantially higher data transfer speeds with reduced static current than existing cross-coupled voltage level shifters. The voltage level shifters disclosed herein include first stage that translates input voltage signals received from a core circuitry in a first voltage domain to intermediate output voltage signals an intermediate voltage domain, and second stage circuitry that translates the intermediate output voltage signals received from the first stage circuitry in the intermediate voltage domain to output voltage signals in a second voltage domain. The disclosed voltage level shifters are scalable to support various logic voltage levels in the second voltage domain.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: SHIV HARIT MATHUR, SAI RAVI TEJA KONAKALLA
  • Patent number: 11916549
    Abstract: Improved voltage level shifters are disclosed capable of achieving substantially higher data transfer speeds with reduced static current than existing cross-coupled voltage level shifters. The voltage level shifters disclosed herein include first stage that translates input voltage signals received from a core circuitry in a first voltage domain to intermediate output voltage signals an intermediate voltage domain, and second stage circuitry that translates the intermediate output voltage signals received from the first stage circuitry in the intermediate voltage domain to output voltage signals in a second voltage domain. The disclosed voltage level shifters are scalable to support various logic voltage levels in the second voltage domain.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: February 27, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shiv Harit Mathur, Sai Ravi Teja Konakalla
  • Publication number: 20230402107
    Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Nitin Gupta, Shiv Harit Mathur, Ramakrishnan Subramanian, Dmitry Vaysman
  • Publication number: 20230350453
    Abstract: Systems and methods disclosed herein provide for an improved glitch-free clock multiplexer exhibiting noise insensitivity with reduced power consumption and reduced physical area on a chip. The embodiments disclosed herein operate without any need of a reference clock. Due to which, clock interchangeability is possible at any point of time. An example glitch-free clock multiplexing according to the embodiments disclosed herein utilize a plurality of clock path circuits, each corresponding to a clock. The clock path circuits are activated responsive to a system startup signal. Based on a clock selection, the embodiments herein deactivate clock path circuits for unselected clocks and, dependent on the deactivation of the unselected clock path circuits, activate clock path circuits of any selected clocks.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: SHIV HARIT MATHUR, Avinash Pandit
  • Patent number: 11803207
    Abstract: Systems and methods disclosed herein provide for an improved glitch-free clock multiplexer exhibiting noise insensitivity with reduced power consumption and reduced physical area on a chip. The embodiments disclosed herein operate without any need of a reference clock. Due to which, clock interchangeability is possible at any point of time. An example glitch-free clock multiplexing according to the embodiments disclosed herein utilize a plurality of clock path circuits, each corresponding to a clock. The clock path circuits are activated responsive to a system startup signal. Based on a clock selection, the embodiments herein deactivate clock path circuits for unselected clocks and, dependent on the deactivation of the unselected clock path circuits, activate clock path circuits of any selected clocks.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: October 31, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shiv Harit Mathur, Avinash Pandit
  • Publication number: 20230198524
    Abstract: An improved cross-coupled voltage level shifter is disclosed that is capable of achieving substantially higher data transfer speeds with reduced transistor sizes than existing cross-coupled voltage level shifters. The voltage level shifter includes a cross-coupled latch, control circuitry that initiates a state transition of the latch responsive to activation, where the control circuitry is activated by a change in a logic voltage level of an input signal to the voltage level shifter, and feedback circuitry that reinforces the latch action of the cross-coupled latch. The control circuitry may include pull-down transistors that are thin-gate devices, and thus, substantially smaller in area than what would otherwise be needed to meet the large current requirement of the pull-down transistors as compared to latch transistors of the latch.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Inventor: Shiv Harit Mathur
  • Patent number: 11539207
    Abstract: Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shiv Harit Mathur, Nitin Gupta
  • Patent number: 11222889
    Abstract: The disclosure relates in some aspects to electrostatic discharge (ESD) protection for an electronic circuit. In some aspects, the ESD protection includes a buffer circuit that increases the slew rate of a signal that controls a discharge circuit. In some aspects, the ESD protection includes a voltage-dependent resistance circuit that adjusts a time constant of a resistive-capacitive filter based on a voltage on a supply node.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: January 11, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shiv Harit Mathur, Ramakrishnan Subramanian
  • Patent number: 11210241
    Abstract: A data storage system includes a storage medium including plurality of memory cells, a storage controller in communication with the storage medium, an electrical interface circuitry configured to pass data via a channel disposed between the storage medium and the storage controller; and voltage training circuitry configured to train a high-level output voltage (VOH) for each of a plurality of data lines of the channel. Training the VOH includes, for each of the plurality of data lines of the channel, calibrating a pull-up driver of the storage controller against an on-die termination circuit of the storage medium, calibrating a pull-down driver of the storage controller against the pull-up driver of the storage controller, and calibrating an on-die termination circuit of the storage controller against a pull-up driver of the storage medium.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: December 28, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Nitin Gupta, Ashish Savadia, Jayanth Thimmaiah, Ramakrishnan Subramanian, Rampraveen Somasundaram, Shiv Harit Mathur, Vinayak Ghatawade, Siddesh Darne, Venkatesh Ramachandra, Elkana Richter
  • Publication number: 20210313802
    Abstract: Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shiv Harit MATHUR, Nitin GUPTA
  • Patent number: 11056880
    Abstract: Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shiv Harit Mathur, Nitin Gupta
  • Patent number: 10878860
    Abstract: A data storage system includes a memory including a plurality of memory cells; and an interface coupled to the memory and a host. The interface includes a multi-level transmission encoder configured to receive an input data signal from the host and encode the input data signal as a multi-level data signal. The interface further includes a multi-stage driver network including a plurality of driver stages, wherein each driver stage of the plurality of driver stages is configured to apply an impedance or forego applying an impedance to the multi-level data signal based on a previous state and a current state of the multi-level data signal.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Nitin Gupta, Shiv Harit Mathur, Ramakrishnan Subramanian