Patents by Inventor Shiv Kumar Mishra
Shiv Kumar Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11508810Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.Type: GrantFiled: November 13, 2020Date of Patent: November 22, 2022Assignee: GLOBALFOUNDRIES INC.Inventors: Jagar Singh, Shiv Kumar Mishra
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Patent number: 11239315Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.Type: GrantFiled: February 3, 2020Date of Patent: February 1, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Shiv Kumar Mishra, Baofu Zhu, Arkadiusz Malinowski, Kaushikee Mishra
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Patent number: 11094822Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.Type: GrantFiled: January 24, 2020Date of Patent: August 17, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Arkadiusz Malinowski, Baofu Zhu, Judson R. Holt, Shiv Kumar Mishra
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Publication number: 20210242306Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.Type: ApplicationFiled: February 3, 2020Publication date: August 5, 2021Inventors: Shiv Kumar MISHRA, Baofu ZHU, Arkadiusz MALINOWSKI, Kaushikee MISHRA
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Publication number: 20210234045Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.Type: ApplicationFiled: January 24, 2020Publication date: July 29, 2021Inventors: Arkadiusz Malinowski, Baofu Zhu, Judson R. Holt, Shiv Kumar Mishra
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Publication number: 20210066450Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Inventors: Jagar SINGH, Shiv Kumar MISHRA
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Patent number: 10896953Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.Type: GrantFiled: April 12, 2019Date of Patent: January 19, 2021Assignee: GLOBALFOUNDRIES INC.Inventors: Jagar Singh, Shiv Kumar Mishra
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Publication number: 20200328272Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.Type: ApplicationFiled: April 12, 2019Publication date: October 15, 2020Inventors: Jagar SINGH, Shiv Kumar MISHRA
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Patent number: 10453747Abstract: Methods of forming a contact for a semiconductor device with double barrier layer sets, and a device so formed are disclosed. Methods may include: depositing a first metal layer contacting a semiconductor substrate in a contact opening; depositing a first nitride barrier layer on the first metal layer; and annealing after depositing the first nitride barrier layer to form silicide region in a junction area underlying the contact opening with the first metal layer and the semiconductor substrate. After the annealing, a second metal layer may be deposited, followed by a second nitride barrier layer. A conductor is formed in a remaining portion of the contact opening. The double barrier layer sets prevent the formation of volcano defects and also advantageously reduce contact resistance.Type: GrantFiled: August 28, 2017Date of Patent: October 22, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Aditya Kumar, Shiv Kumar Mishra, Jean-Baptiste Jacques Laloë, Wen Zhi Gao
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Patent number: 10236367Abstract: A device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction. The second well includes a silicon alloy portion displaced from the PN junction. A collector region contacts one of the first or second wells and has a dopant concentration higher than its contacted well. An emitter region contacts the other of the first or second wells and is doped with dopants of the first or second conductivity type different than the first or second well contacted by the emitter region. A base region contacts the other of the first or second well and has a dopant concentration higher than the first or second well contacted by the base region.Type: GrantFiled: July 6, 2017Date of Patent: March 19, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Jagar Singh, Shiv Kumar Mishra
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Publication number: 20190067098Abstract: Methods of forming a contact for a semiconductor device with double barrier layer sets, and a device so formed are disclosed. Methods may include: depositing a first metal layer contacting a semiconductor substrate in a contact opening; depositing a first nitride barrier layer on the first metal layer; and annealing after depositing the first nitride barrier layer to form silicide region in a junction area underlying the contact opening with the first metal layer and the semiconductor substrate. After the annealing, a second metal layer may be deposited, followed by a second nitride barrier layer. A conductor is formed in a remaining portion of the contact opening. The double barrier layer sets prevent the formation of volcano defects and also advantageously reduce contact resistance.Type: ApplicationFiled: August 28, 2017Publication date: February 28, 2019Inventors: Aditya Kumar, Shiv Kumar Mishra, Jean-Baptiste Jacques Laloë, Wen Zhi Gao
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Publication number: 20190013402Abstract: A semiconductor device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction between the first and second wells. The second well includes a silicon alloy portion displaced from the PN junction. A source region is positioned in one of the first well or the second well. A drain region is positioned in the other of the first well or the second well. A gate structure is positioned above the substrate laterally positioned between the source region and the drain region.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Inventors: Jagar Singh, Shiv Kumar Mishra
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Publication number: 20190013397Abstract: A device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction. The second well includes a silicon alloy portion displaced from the PN junction. A collector region contacts one of the first or second wells and has a dopant concentration higher than its contacted well. An emitter region contacts the other of the first or second wells and is doped with dopants of the first or second conductivity type different than the first or second well contacted by the emitter region. A base region contacts the other of the first or second well and has a dopant concentration higher than the first or second well contacted by the base region.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Inventors: Jagar Singh, Shiv Kumar Mishra
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Patent number: 10084093Abstract: During formation of a trench silicide contact, a sacrificial layer is incorporated into the trench directly over source/drain junctions prior to metallization of the trench. Selective removal of the sacrificial layer widens the trench proximate to the source/drain junctions, increasing the contact area and correspondingly decreasing the contact resistance between the source/drain junctions and a silicide layer.Type: GrantFiled: May 22, 2017Date of Patent: September 25, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Shiv Kumar Mishra, Sunil Kumar Singh, Shesh Mani Pandey
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Patent number: 9419082Abstract: P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.Type: GrantFiled: April 23, 2014Date of Patent: August 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Shiv Kumar Mishra, Zhiqing Li, Scott Beasor, Shesh Mani Pandey
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Patent number: 9236269Abstract: Approaches for providing a fin field effect transistor device (FinFET) with a planar block area to enable variable fin pitch and width are disclosed. Specifically, approaches are provided for forming a plurality of fins patterned from a substrate, the plurality of fins comprising: a first set of fins having a variable pitch and a variable width; and a second set of fins having a variable pitch and a uniform width, wherein the first set of fins is adjacent the second set of fins. In one approach, the first set of fins is patterned from the planar block area, which is formed over the substrate, and the second set of fins is formed using a sidewall image transfer (SIT) process.Type: GrantFiled: April 23, 2014Date of Patent: January 12, 2016Assignee: GlobalFoundries Inc.Inventors: Eric S. Kozarsky, Shiv Kumar Mishra
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Publication number: 20150311293Abstract: P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.Type: ApplicationFiled: April 23, 2014Publication date: October 29, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Shiv Kumar MISHRA, Zhiqing LI, Scott BEASOR, Shesh Mani PANDEY
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Publication number: 20150311085Abstract: Approaches for providing a fin field effect transistor device (FinFET) with a planar block area to enable variable fin pitch and width are disclosed. Specifically, approaches are provided for forming a plurality of fins patterned from a substrate, the plurality of fins comprising: a first set of fins having a variable pitch and a variable width; and a second set of fins having a variable pitch and a uniform width, wherein the first set of fins is adjacent the second set of fins. In one approach, the first set of fins is patterned from the planar block area, which is formed over the substrate, and the second set of fins is formed using a sidewall image transfer (SIT) process.Type: ApplicationFiled: April 23, 2014Publication date: October 29, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Eric S. Kozarsky, Shiv Kumar Mishra