Abstract: A circuit comprising a plurality of gates and a plurality of control circuits. The plurality of gates may each have an output connected to an input of a next gate of the plurality of gates. The plurality of control circuits may be connected to a second input of one or more gates of the plurality of gates. The plurality of control circuits may simulate switching.

Abstract: A programmable interconnect matrix (PIM) design, layout, schematic, netlist, abstract or other equivalent circuit representation (hereinafter “layout”) is hierarchically generated by selecting one or more PIM layout tiles from a plurality of different PIM layout tiles, and automatically compiling a plurality of the selected PIM layout tiles into a PIM layout. In some cases, the PIM layout tiles can be heterogeneous. Generally, the PIM layout includes a PIM array having one of a plurality of different sizes (e.g., n rows by m columns, n and m>1). In other embodiments, a PIM connection scheme is generated by automatically compiling a plurality of PIM layout tiles into a PIM layout, then programming interconnects of the PIM according to a mapping table specifying desired interconnections. This scheme may include generating the mapping table with software configured to optimize connections and/or routability and/or automatically generating a PIM layout database from the PIM connection scheme.

Abstract: A design, layout, schematic, netlist, abstract or other equivalent circuit representations for a memory that may have redundant circuitry may be generated from a set of user inputs acquired through a graphical user interface. Based on the user inputs one or more leaf cells is/are generated. Then using the leaf cells, a design database for the layout is generated from the user inputs. The design database reflects physical hierarchies of the layout and may include redundancy circuitry within a data and/or address path, parallel to a non-redundant data and/or address path within the layout. The above-mentioned parameters described by the user inputs may include an array size, a defect rate, and/or a leaf cell design, layout or schematic. This scheme may be embodied as a set of computer-readable instructions, for example to be executed by a computer system.

Abstract: A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors that are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.

Abstract: A write control circuit for a semiconductor memory device includes a conventional write path responsive to a control input (e.g., an external write enable signal) to control the beginning of a write operation for a write driver, whilst a separate dedicated write disable path, responsive to the same control input, controls the end of the write operation for the write driver. The invention separates the end of write from the beginning of write by introducing a fast dedicated path designed primarily for ending the write. This dedicated path contains dedicated logic to generate an end of write signal at the disabling edge of the control input to disable the write driver quickly before a new memory cell is selected.

Abstract: A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors which are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.

Abstract: The generation of a controlled voltage signal as a buffer control signal for an output driver provides for relatively less delay for a high output enable access for an output buffer. As the output buffer undergoes the transition from a deselected state to a selected state to generate an output signal corresponding to a high input signal, a first voltage level is generated at a node and output as the control signal for the output driver, providing for an initial pull-up transition for the output signal. A second voltage level is subsequently generated at the node and output as the control signal for the output driver, providing for a steady-state voltage level for the high output signal.

Abstract: A programmable logic device (PLD) architecture that minimizes the skew in the outputs of PLD devices in response to input signal transitions. The architecture emulates the worst case response condition of the memory array portion of the PLD and builds it into a dedicated emulation signal path, which is in parallel with the signal path of the real data between the input and output of the PLD. The output of the emulation signal path then controls the real data output path and thus the output of the PLD. The PLD output equals the real data path output only when the output of the emulation signal path is valid.

Abstract: A pull-down output device controls the discharge of an output signal for a pull-down transition. A pull-down control signal is generated in response to an input signal. A control signal is generated in response to the pull-down control signal to couple a first voltage terminal to a control signal node. The output signal is initially discharged as a bipolar transistor is turned-on by the control signal at the node and couples the output signal to a second voltage terminal. The first voltage terminal is decoupled from the control signal node as a control signal is generated to couple the output signal to the control signal node. The output signal is further discharged through the bipolar transistor. The discharge of the output signal is thus controlled.

Abstract: A power reduction circuit for selectively providing power to circuitry associated with and coupled to the power reduction circuit, which includes two transistors having current paths coupled in parallel and a nonvolatile programmable storage device having a current path coupled in series with the current paths of the two transistors. A control transistor which is also part of the power reduction circuit includes a current path between a power supply and the circuitry associated with and coupled to the power reduction circuit to selectively provide power to the associated circuitry. The control transistor has a control gate electrode which is coupled between the current path of the nonvolatile programmable storage device and the current paths of the two transistors. The state of the storage device controls the state of the control gate electrode of the control transistor and accordingly controls whether the power is supplied to the associated circuitry.