Patents by Inventor Shiva Sorooshian Borzin

Shiva Sorooshian Borzin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6243664
    Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width wmux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width wmux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: June 5, 2001
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hagop A. Nazarian, Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin, Darren Neuman
  • Patent number: 5923868
    Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: July 13, 1999
    Assignee: Cypress Semiconductor Corp.
    Inventors: Hagop A. Nazarian, Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin, Darren Newman
  • Patent number: 5848066
    Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: December 8, 1998
    Assignee: Cypress Semiconductor Corp.
    Inventors: Hagop A. Nazarian, Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin, Darren Neuman
  • Patent number: 5689686
    Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: November 18, 1997
    Assignee: Cypress Semiconductor Corp.
    Inventors: Hagop A. Nazarian, Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin, Darren Neuman