Abstract: An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.

Abstract: A delay lock loop (DLL) system includes a master DLL and at least one slave DLL. The master DLL comprises a master delay line, a phase detector, and a loop controller. The master delay line of the master DLL includes four quarter cycle delay lines (QCDL). The slave DLL comprises a delay line and a fractional bit delay element. The delay line of the slave DLL is controlled by the slave delay line control signal generated by the loop controller of the master DLL. The final output of the slave DLL is formed such that the output of the delay line of the slave DLL is corrected by the fractional bit delay generated by the factional bit delay element such that the final output of the slave DLL has a finer delay line resolution than the one of the output of the delay line of the slave DLL.

Abstract: An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.