Abstract: In view of the foregoing, an embodiment herein provides a low cost system. The system includes a bipolar array, a CMOS chip. The bipolar array includes one or more bipolar integrated circuits. The CMOS chip is programmed by a single level of metal. The bipolar array and the CMOS chip is mounted on a substrate using TAB polyamide. The TAB includes a polyamide film with one or more metal patterns chemically etched by programming three metal layers simultaneously to obtain one or more components. The one or more components are mounted in a package, and a small system can be realized. An external capacitor supplies an ac power source to the bipolar array. The bipolar array produces a rectified voltage and a lower voltage power for the enhanced gate array. An output of the enhanced gate array drives bipolar drivers of DC motor, stepper motor, BLDC motor, and LED assemblies.

Abstract: In apparatus for digital processing to a sequence of numbers in binary format, each number is first converted to a base number and a residue number, the residue number being in a binary bit format. The processing is then performed using only the residue numbers. The digital processing is perfumed using binary addition, binary subtraction, and binary multiplication operations. After completion of the processing operation, the residue numbers are then converted into the original format. The folding analog-to-digital converter can be used to generate the residue binary bit numbers from an analog signal. This technique can reduce the apparatus required to perform such processing operations as FIR filtering and equalization.

Abstract: A digital filter can be implemented with a reduced number of components for a transform function having specific characteristics in the regions outside of a center region. The characteristics are that the transform function waveform is periodic with period T and has or can be approximated by at least one envelope, the envelope decaying a multiplier constant for each period T in a direction away from the waveform center. The digital filter has three groups of elements. A center group of components functions in a manner similar to the prior digital filters. A positive time group of components receives the signals from the center, and using a group of delay component, delays the signal by one period T, is reduced by the multiplier constant factor, and after having the current signal from the center group applied thereto, is once again applied to the positive time group delay components.

Abstract: A metal-oxide-semiconductor digital-to-analog converter unit includes a multiplicity of current mirror components 20 in a symmetric array, a resistance network activated by voltage sources providing weighted biasing potentials for the current mirror components, and an electrical coupling of the current mirror components to compensate for variations physical properties across converter unit substrate area. The current mirror components 20 include a current steering portion 21.sub.0 -21.sub.N-1 and 25.sub.0 -25.sub.N-1 coupled to an annular bias transistor 22. The resulting digital-to-analog converter has improved performance characteristics when compared to previously implemented digital-to-analog converter units.

Abstract: A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 2,200 boolean combinational functions on output 431, to operate as a full adder with sum and carry outputs, or to perform the sequential function of a D latch or a D flipflop. Logic module 400 is comprised of 2-input multiplexers 500 and 600 which are used to form both the combinational and sequential circuits, thereby efficiently utilizing space on gate array 100.

Abstract: A multiplier and method of multiplying a multiplicand by a multiplier comprising providing a multiplicand of predetermined radix, preferably two, and a predetermined multiple of the multiplicand, preferably three, of the predetermined radix. First and second paths are provided, each path including the multiplicand and the multiple of the multiplicand. One of the multiplicand or multiple of the multiplicand in said first path is selected responsive to the value of the multiplier and one of the multiplicand or multiple of the multiplicand in the second path is selected responsive to the value of the multiplier. The selected multiplicand or multiple of the multiplicand in said first path is left shifted a number of shifts determined by the value of the multiplier and the selected multiplicand or multiple of the multiplicand in the second path is left shifted a number of shifts determined by the value of the multiplier.

Abstract: A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal.

Abstract: A method for forming a gate array substrate contact and the contact resulting therefrom includes the steps of etching off polysilicon gate layers at the same time as cutting the polysilicon to form the gate array base cell (10). The method includes forming openings (40, 42, and 44) in the second insulating layer (34) and insulating layer (30) to connect a lead (46, 48, and 50) to the underlying substrate.

Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.

Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.

Abstract: A memory system 10 is provided including a processor 12 and an active memory device 14 coupled to a processor 12. Active memory 14 includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12. Circuitry 26 is provided for identifying at least one active address from ones of the possible addresses stored in first memory 20 as a function of the actual address stored in second memory 22.

Abstract: A bipolar transistor is disclosed which substantially reduces prior art problems associated with current crowding by maximizing the active periphery of the transistor's emitter [10].