Patents by Inventor Shivaling Shrishail Mahant Shetti

Shivaling Shrishail Mahant Shetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9966792
    Abstract: An uninterruptible power supply circuit is provided. The uninterruptible power supply circuit includes a first diode, a second diode, a bridge rectifier, and one or more electrical loads. The first diode, the second diode, the bridge rectifier, and the one or more electrical loads are electrically connected in the uninterruptible power supply circuit to drive the one or more electrical loads with a DC voltage or the intended AC supply voltage when the AC supply voltage is cutoff.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: May 8, 2018
    Inventor: Shivaling Shrishail Mahant Shetti
  • Patent number: 9755642
    Abstract: In view of the foregoing, an embodiment herein provides a low cost system. The system includes a bipolar array, a CMOS chip. The bipolar array includes one or more bipolar integrated circuits. The CMOS chip is programmed by a single level of metal. The bipolar array and the CMOS chip is mounted on a substrate using TAB polyamide. The TAB includes a polyamide film with one or more metal patterns chemically etched by programming three metal layers simultaneously to obtain one or more components. The one or more components are mounted in a package, and a small system can be realized. An external capacitor supplies an ac power source to the bipolar array. The bipolar array produces a rectified voltage and a lower voltage power for the enhanced gate array. An output of the enhanced gate array drives bipolar drivers of DC motor, stepper motor, BLDC motor, and LED assemblies.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: September 5, 2017
    Inventor: Shivaling Shrishail Mahant Shetti
  • Patent number: 9595953
    Abstract: A circuit for automatically compensating beta variation by driving base of BJT with JFET is disclosed. The circuit includes a first well, a second well, a third well, one or more leakage current devices, and a varying metal connection. The first well includes first JFET J1, second JFET J2, third JFET J3 and fourth JFET J4. The input voltage value is combination of emitter to base voltage of first BJT Q1, emitter to base voltage of second BJT Q2. The second well includes first BJT Q1, second BJT Q2 and second diode D2. The third well includes first diode snubber D1. The one or more leakage current devices are connected between base of Q1 and base Q2 to remove excess leakage current across the second well. The varying metal connection is connected across the first well, the second well and the third well to obtain beta value.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: March 14, 2017
    Inventor: Shivaling Shrishail Mahant Shetti
  • Publication number: 20160163736
    Abstract: A system for implementing an integrated circuit(IC) is provided. The system includes one or more base layers. By using one or more single base layers integrated circuit can be made for a high-speed CMOS (HC) and high-speed CMOS TTL (transistor-transistor logic) compatible (HCT) families. A base layers may be fixed and just one or more metal patterns may be changed for respective integrated circuit (IC). A wafer bank includes large number of transistors to implement one or more circuits by changing the metal pattern required and can make the required circuit.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 9, 2016
    Inventor: Shivaling Shrishail Mahant Shetti
  • Publication number: 20160164512
    Abstract: A circuit for automatically compensating beta variation by driving base of BJT with JFET is disclosed. The circuit includes a first well, a second well, a third well, one or more leakage current devices, and a varying metal connection. The first well includes first JFET J1, second JFET J2, third JFET J3 and fourth JFET J4. The input voltage value is combination of emitter to base voltage of first BJT Q1, emitter to base voltage of second BJT Q2. The second well includes first BJT Q1, second BJT Q2 and second diode D2. The third well includes first diode snubber D1. The one or more leakage current devices are connected between base of Q1 and base Q2 to remove excess leakage current across the second well. The varying metal connection is connected across the first well, the second well and the third well to obtain beta value.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 9, 2016
    Inventor: Shivaling Shrishail Mahant Shetti
  • Publication number: 20160141917
    Abstract: An uninterruptible power supply circuit is provided. The uninterruptible power supply circuit includes a first diode, a second diode, a bridge rectifier, and one or more electrical loads. The first diode, the second diode, the bridge rectifier, and the one or more electrical loads are electrically connected in the uninterruptible power supply circuit to drive the one or more electrical loads with a DC voltage or the intended AC supply voltage when the AC supply voltage is cutoff.
    Type: Application
    Filed: November 19, 2015
    Publication date: May 19, 2016
    Inventor: Shivaling Shrishail Mahant Shetti