Patents by Inventor Shivam Agrawal

Shivam Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12149255
    Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.
    Type: Grant
    Filed: January 10, 2024
    Date of Patent: November 19, 2024
    Assignee: Shaoxing Yuanfang Semiconductor Co., Ltd.
    Inventors: Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Kumar Gupta, Nitesh Naidu, Shivam Agrawal, Jeevabharathi G, Purva Choudhary
  • Publication number: 20240154617
    Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Inventors: Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Kumar Gupta, Nitesh Naidu, Shivam Agrawal, Jeevabharathi G, Purva Choudhary
  • Patent number: 11967965
    Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: April 23, 2024
    Assignee: Shaoxing Yuanfang Semiconductor Co., Ltd.
    Inventors: Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Kumar Gupta, Nitesh Naidu, Shivam Agrawal, Jeevabharathi G, Purva Choudhary
  • Publication number: 20230136353
    Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.
    Type: Application
    Filed: June 14, 2022
    Publication date: May 4, 2023
    Inventors: Raja Prabhu J, Ankit Seedher, Srinath Sridharan, Rakesh Kumar Gupta, Nitesh Naidu, Shivam Agrawal, Jeevabharathi G, Purva Choudhary
  • Patent number: 11588489
    Abstract: A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 21, 2023
    Assignee: Shaoxing Yuanfang Semiconductor Co., Ltd.
    Inventors: Rakesh Kumar Gupta, Nitesh Naidu, Raja Prabhu J, Srinath Sridharan, Ankit Seedher, Shivam Agrawal
  • Publication number: 20220180019
    Abstract: Systems and methods generate and use a digital twin in a hydrocarbon system. The systems and methods can perform the following operations: (1) performing a plurality of simulations in a hyperdimensional space to generate outputs; (2) using the outputs of the plurality of simulations to generate one or more reduced order models (ROMs) using a regression technique or a machine learning technique; (3) generating a digital twin of the hydrocarbon system by instantiating the one or more ROMs at an operational point of the hydrocarbon system, and configuring the digital twin to use real-time data obtained from the hydrocarbon system; and (4) estimating values of one or more variables of the hydrocarbon system in real-time using the digital twin.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 9, 2022
    Inventors: Jonathan Chong, Albert Hoefel, Nam Nguyen, Rongzhen Jin, Shivam Agrawal, Yves-Marie Subervie