Patents by Inventor Shivam Swami
Shivam Swami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152464Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).Type: ApplicationFiled: January 5, 2024Publication date: May 9, 2024Inventors: Kenneth Marion Curewitz, Sean Stephen Eilert, Hongyu Wang, Samuel E. Bradshaw, Shivasankar Gunasekaran, Justin M. Eno, Shivam Swami
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Publication number: 20240143196Abstract: Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.Type: ApplicationFiled: September 8, 2023Publication date: May 2, 2024Inventors: Richard C. Murphy, Shivam Swami, Naveh Malihi, Anton Korzh, Glen E. Hush
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Patent number: 11960738Abstract: Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task.Type: GrantFiled: October 27, 2022Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventors: Shivam Swami, Kenneth Marion Curewitz
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Patent number: 11947453Abstract: An example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.Type: GrantFiled: November 20, 2020Date of Patent: April 2, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Sean S. Eilert, Ameen D. Akel, Shivam Swami
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Patent number: 11868268Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).Type: GrantFiled: February 7, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Kenneth Marion Curewitz, Sean S. Eilert, Hongyu Wang, Samuel E. Bradshaw, Shivasankar Gunasekaran, Justin M. Eno, Shivam Swami
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Publication number: 20230393992Abstract: Row hammer attacks takes advantage of unintended and undesirable side effects of memory devices in which memory cells interact electrically between themselves by leaking their charges and possibly changing the contents of nearby memory rows that were not addressed in an original memory access. Row hammer attacks are mitigated by using a victim cache. Data is written to cache lines of a cache. A least recently used cache line of the cache is written to the victim cache.Type: ApplicationFiled: September 15, 2022Publication date: December 7, 2023Inventors: Ameen D. Akel, Shivam Swami
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Patent number: 11755210Abstract: Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.Type: GrantFiled: February 4, 2022Date of Patent: September 12, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Shivam Swami, Naveh Malihi, Anton Korzh, Glen E. Hush
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Publication number: 20230236747Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.Type: ApplicationFiled: March 27, 2023Publication date: July 27, 2023Inventors: Kenneth Marion Curewitz, Shivasankar Gunasekaran, Ameen D. Akel, Hongyu Wang, Justin M. Eno, Shivam Swami, Samuel E. Bradshaw
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Patent number: 11650742Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.Type: GrantFiled: September 17, 2019Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Kenneth Marion Curewitz, Shivasankar Gunasekaran, Ameen D. Akel, Hongyu Wang, Justin M. Eno, Shivam Swami, Samuel E. Bradshaw
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Patent number: 11636893Abstract: An example memory sub-system includes: a plurality bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each bank group; and a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving, from a host, a command identifying a row buffer of the plurality of row buffers; and perform an operation with respect to the identified row buffer.Type: GrantFiled: October 19, 2020Date of Patent: April 25, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Sean S. Eilert, Ameen D. Akel, Shivam Swami
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Publication number: 20230046808Abstract: Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task.Type: ApplicationFiled: October 27, 2022Publication date: February 16, 2023Inventors: Shivam Swami, Kenneth Marion Curewitz
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Publication number: 20230033549Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.Type: ApplicationFiled: October 12, 2022Publication date: February 2, 2023Inventors: Samuel E. Bradshaw, Justin M. Eno, Sean Stephen Eilert, Shivasankar Gunasekaran, Hongyu Wang, Shivam Swami
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Patent number: 11556656Abstract: Methods and apparatus of Exclusive OR (XOR) engine in a random access memory device to accelerate cryptographical operations in processors. For example, an integrated circuit memory device enclosed within a single integrated circuit package can include an XOR engine that is coupled with memory units in the random access memory device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., System-on-Chip (SoC) or Central Processing Unit (CPU)) can have encryption logic that performs cryptographical operations using XOR operations that are performed by the XOR engine in the random access memory device using the data in the random access memory device.Type: GrantFiled: September 25, 2019Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Shivam Swami, Sean S. Eilert, Ameen D. Akel, Kenneth Marion Curewitz, Hongyu Wang
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Publication number: 20220391330Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.Type: ApplicationFiled: August 15, 2022Publication date: December 8, 2022Inventors: Samuel E. Bradshaw, Shivam Swami, Sean Stephen Eilert, Justin M. Eno, Ameen D. Akel
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Publication number: 20220392509Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).Type: ApplicationFiled: June 22, 2022Publication date: December 8, 2022Inventors: Shivam Swami, Sean S. Eilert, Ameen D. Akel
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Patent number: 11500555Abstract: Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task.Type: GrantFiled: September 4, 2020Date of Patent: November 15, 2022Assignee: Micron Technology, Inc.Inventors: Shivam Swami, Kenneth Marion Curewitz
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Patent number: 11494311Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.Type: GrantFiled: September 17, 2019Date of Patent: November 8, 2022Assignee: Micron Technology, Inc.Inventors: Samuel E. Bradshaw, Justin M. Eno, Sean S. Eilert, Shivasankar Gunasekaran, Hongyu Wang, Shivam Swami
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Patent number: 11416422Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.Type: GrantFiled: September 17, 2019Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Samuel E. Bradshaw, Shivam Swami, Sean S. Eilert, Justin M. Eno, Ameen D. Akel
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Patent number: 11373695Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).Type: GrantFiled: December 18, 2019Date of Patent: June 28, 2022Assignee: Micron Technology, Inc.Inventors: Shivam Swami, Sean S. Eilert, Ameen D. Akel
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Publication number: 20220155978Abstract: Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.Type: ApplicationFiled: February 4, 2022Publication date: May 19, 2022Inventors: Richard C. Murphy, Shivam Swami, Naveh Malihi, Anton Korzh, Glen E. Hush