Abstract: Systems, methods, and devices prevent data loss in memory devices. Systems may include a non-volatile memory device that includes a first data unit configured to store data for the non-volatile memory device and associated metadata, and a second data unit configured to store data for the non-volatile memory device and associated metadata, wherein the first data unit and second data unit are configured to alternate storing a most recent version of the data and associated metadata. The systems may also include control circuitry configured to read metadata from the first data unit and the second data unit, identify the first data unit as an inactive data unit based on contents of the first data unit and the second data unit, and perform one or more update operations such that the first data unit is updated and set as an active unit when the update operations are complete.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor device may include a first region including at least one non-volatile memory (NVM) transistor having a lower source/drain (S/D) junction and an upper S/D junction, a vertical channel disposed between the upper and lower S/D junctions and surrounded by a cylindrical memory film stack, and a gate layer disposed around the memory film stack, the device also include a second region including at least one logic transistor each having a gate dielectric layer overlying a horizontal channel, a gate layer, and a height-enhancement layer. Other embodiments are also described.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may include a non-volatile memory (NVM) transistor form over a substrate having a buried lower source/drain (S/D) junction, an upper S/D junction, a vertical channel having a cylindrical shape disposed between the upper and lower S/D junctions, a cylindrical memory film stack surrounding the vertical channel, and a gate layer disposed around the memory film stack. The semiconductor devices may also include word lines surrounding the vertical channels, bit lines and source lines connecting multiple NVM transistors. Other embodiments are also described.

Abstract: Systems, methods, and devices prevent data loss in memory devices. Systems may include a non-volatile memory device that includes a first data unit configured to store data for the non-volatile memory device and associated metadata, and a second data unit configured to store data for the non-volatile memory device and associated metadata, wherein the first data unit and second data unit are configured to alternate storing a most recent version of the data and associated metadata. The systems may also include control circuitry configured to read metadata from the first data unit and the second data unit, identify the first data unit as an inactive data unit based on contents of the first data unit and the second data unit, and perform one or more update operations such that the first data unit is updated and set as an active unit when the update operations are complete.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Abstract: A system and method are provided for generating a Physical Unclonable Function (PUF) for a semiconductor memory to a host processing system. Generally, the method involves allocating a number of memory cells in a memory device; performing a bitmap readout at a median threshold voltages (VT) of cells to generate a multibit Binary Entropy String (BES). Unstable bits in the BES are identified, and a mask of cell locations associated with the unstable bits generated. The BES is multiplied with the mask to generate a Physical Unclonable Function (PUF) including a Binary String of stable bits, and error-correction performed on the Binary String to generate ECC data. The mask and ECC data are stored in the memory device, and are used to regenerate the PUF to authenticate and uniquely identity the memory device to a host processing system. Various methods for generating the mask are disclosed.

Abstract: A method of operating a memory circuit is disclosed. The memory circuit includes a memory array having a memory portion and a spare portion. The method includes receiving a first write command to a first memory address, where the first memory address has a status of being mapped to a first spare memory address, and where the first memory address corresponds to a first memory location in the memory portion and the first spare memory address corresponds to a first spare memory location in the spare portion. The method also includes performing, in response to the first write command, a first write operation by attempting to write first data to the first memory location, determining if the first write operation is successful, and unmapping, in response to the first write operation of being successful, the first memory address from the first spare memory address.

Abstract: A method of operating a memory circuit is disclosed. The memory circuit includes a memory array having a memory portion and a spare portion. The method includes receiving a first write command to a first memory address, where the first memory address has a status of being mapped to a first spare memory address, and where the first memory address corresponds to a first memory location in the memory portion and the first spare memory address corresponds to a first spare memory location in the spare portion. The method also includes performing, in response to the first write command, a first write operation by attempting to write first data to the first memory location, determining if the first write operation is successful, and unmapping, in response to the first write operation of being successful, the first memory address from the first spare memory address.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Abstract: Systems, methods, and devices implement counters with fault tolerance and power loss protection. Systems include a non-volatile memory device that includes a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing an initiation and a completion of each erase operation performed on the first counter. Systems also include control circuitry configured to generate a count value based on a current counter value of the first counter, a current counter value of the second counter, and at least one physical parameter of the first counter.

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Abstract: Systems, methods, and devices prevent data loss in memory devices. Systems may include a non-volatile memory device that includes a first data unit configured to store data for the non-volatile memory device and associated metadata, and a second data unit configured to store data for the non-volatile memory device and associated metadata, wherein the first data unit and second data unit are configured to alternate storing a most recent version of the data and associated metadata. The systems may also include control circuitry configured to read metadata from the first data unit and the second data unit, identify the first data unit as an inactive data unit based on contents of the first data unit and the second data unit, and perform one or more update operations such that the first data unit is updated and set as an active unit when the update operations are complete.

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.

Abstract: Systems, methods, and devices implement counters with fault tolerance and power loss protection. Systems include a non-volatile memory device that includes a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing an initiation and a completion of each erase operation performed on the first counter. Systems also include control circuitry configured to generate a count value based on a current counter value of the first counter, a current counter value of the second counter, and at least one physical parameter of the first counter.

Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.

Abstract: Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Abstract: Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.