Patents by Inventor Shivangi Mittal

Shivangi Mittal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Read-write architecture for low voltage SRAMs
    Patent number: 10790013
    Abstract: An SRAM cell in a bit interleaved memory architecture with two phase sequential write scheme to achieve 100% write ability and the SNM target with bit interleaved architecture in SRAM.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 29, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Prashant Dubey, Ishita Satishchandra Desai, Shivangi Mittal, Surya Prakash Gupta, Jamil Kawa
  • Data storage element and signal processing method
    Patent number: 9602085
    Abstract: A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT1 , DOUT2) have the same logical state, and with a second logical state they have different logical states.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: March 21, 2017
    Assignee: Synopsys, Inc.
    Inventors: Prashant Dubey, Shivangi Mittal, Raushan Kumar Jha
  • Data Storage Element and Signal Processing Method
    Publication number: 20160126936
    Abstract: A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT1, DOUT2) have the same logical state, and with a second logical state they have different logical states.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 5, 2016
    Inventors: Prashant Dubey, Shivangi Mittal, Raushan Kumar Jha