Patents by Inventor Shivani Srivastava
Shivani Srivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074159Abstract: A variety of applications can include apparatus having a memory device with metal digit lines for various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region. In the integrated process flow, material of the metal digit lines can be used as the metal contacts to the transistors in the periphery to the memory array region. In various embodiments, a metal contact can contact a metal gate of a transistor in the periphery or contact a metal barrier region, where the metal barrier region is above and contacting the metal gate and is structured without including polysilicon. Sacrificial polysilicon can be used to protect the gate of the transistor during processing in the memory array region.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Shivani Srivastava, Russell Allen Benson, Raghunath Singanamalla
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Publication number: 20240074160Abstract: A variety of applications can include apparatus having a memory device structured from integrated processing of a memory array of the memory device with a periphery to the memory array. The memory device can be implemented with transistors formed in the periphery, where metal gates of the transistors are structured without polysilicon regions between the metal gates and metal contacts for the metal gates. The integrated processing can provide step height reduction between the memory array and the periphery to the memory array of a memory device, with the elimination of polysilicon on the gate stack of transistors in the periphery. The step height reduction in the memory device can lower overlap capacitance.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Shivani Srivastava, Russell Allen Benson, Raghunath Singanamalla, Jaydeb Goswami
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Publication number: 20240074166Abstract: A variety of applications can include apparatus having a memory device with metal digit lines coupled to various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region, with a metal silicide formed on the gates of the transistors. The metal silicide for each transistor can be coupled to the metal contact for the transistor. In the integrated process flow, material of the metal digit lines can be used as the metal contact to the transistors in the periphery to the memory array region. The metal silicide can be formed by conversion of polysilicon formed on the memory array region and the periphery to the memory array region in the integrated process flow.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Shivani Srivastava, Raghunath Singanamalla, Russell Allen Benson
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Publication number: 20240074161Abstract: A variety of applications can include apparatus having a memory device with digit line contacts disposed in a dielectric and metal digit lines coupled to various of the digit line contacts by at most one metal barrier above the dielectric. Material of the metal digit lines is used as a contact metal to a transistor in a periphery to the memory array region, where the transistor is coupled to the metal contact by multiple barrier metals on polysilicon on the transistor. An integration flow of metallization for periphery devices to a memory array and digit lines can be implemented to allow separate barrier metal formation between the memory array and the periphery, while still using the same material as the main conductor. Barrier metals can be formed for the periphery and the memory array region and then cleared from the memory array region before forming the main conductor.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Russell Allen Benson, Shivani Srivastava, Jaydip Guha, Raghunath Singanamalla
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Publication number: 20240055523Abstract: Electronic devices and methods are disclosed, including transistors with thick gate dielectric layers. Selected devices and methods shown include multiple layer gate dielectrics. Selected devices and methods shown include a gate dielectric with a first layer having a first width, and a second layer over the first layer, wherein the second layer has a second width smaller than the first width.Type: ApplicationFiled: August 9, 2022Publication date: February 15, 2024Inventors: Bingwu Liu, Shivani Srivastava, Dan Mihai Mocuta
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Patent number: 11811874Abstract: Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.Type: GrantFiled: April 13, 2022Date of Patent: November 7, 2023Assignee: Micron Technology, Inc.Inventors: Sharmila Velamur, Fatma Arzum Simsek-Ege, Shivani Srivastava, Marsela Pontoh, Lavanya Sriram
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Publication number: 20230335582Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include semiconductor devices having two or more fins, the fins separated by one or more inter-fin trenches. An isolation structure is included adjacent to the two or more fins, the isolation structure having a depth greater than the inter-fin trench depth.Type: ApplicationFiled: April 13, 2022Publication date: October 19, 2023Inventors: Shivani Srivastava, Toshihiko Miyashita, Dan Mihai Mocuta, Bingwu Liu, Stephen David Snyder
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Publication number: 20230265188Abstract: The invention provides a method of treating a hepatocellular carcinoma with a LAG-3 antagonist alone or in combination with an additional therapeutic agent.Type: ApplicationFiled: August 27, 2021Publication date: August 24, 2023Applicant: Bristol-Myers Squibb CompanyInventors: Shivani SRIVASTAVA, Rebecca A. MOSS, Andrea HORVATH
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Publication number: 20230141716Abstract: Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.Type: ApplicationFiled: November 5, 2021Publication date: May 11, 2023Inventors: Hyuck Soo Yang, Byung Yoon Kim, Yong Mo Yang, Shivani Srivastava
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Publication number: 20220411499Abstract: The disclosure provides a method of treating unresectable or metastatic melanoma in a human patient with a lymphocyte activation gene-3 (LAG-3) antagonist. In some aspects, the method includes a combination of the LAG-3 antagonist with a cytotoxic T-lymphocyte antigen-4 (CTLA-4) inhibitor. In some aspects, the method includes one or more additional therapeutic agents and/or anti-cancer therapies.Type: ApplicationFiled: November 6, 2020Publication date: December 29, 2022Applicant: Bristol-Myers Squibb CompanyInventors: Shivani SRIVASTAVA, Mena ABASKHAROUN
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Publication number: 20220329657Abstract: Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.Type: ApplicationFiled: April 13, 2022Publication date: October 13, 2022Inventors: Sharmila Velamur, Fatma Arzum Simsek-Ege, Shivani Srivastava, Marsela Pontoh, Lavanya Sriram
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Patent number: 11351163Abstract: The disclosure is directed to methods of treating cancer in subjects with a combination of a monoclonal antibody and (R)-N-(4-chlorophenyl)-2-(cis-4-(6-fluoroquinolin-4-yl)cyclohexyl)propanamide, or a salt thereof.Type: GrantFiled: September 28, 2018Date of Patent: June 7, 2022Assignee: Bristol-Myers Squibb CompanyInventors: Paul Andrew Basciano, Justine Kamilah Walker, Penny E. Phillips, Li Zhu, Steven H. Bernstein, James Cassidy, Katy Lynn Simonsen, Alexander Azrilevich, Shivani Srivastava
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Patent number: 11323521Abstract: Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.Type: GrantFiled: April 8, 2021Date of Patent: May 3, 2022Assignee: Micron Technology, Inc.Inventors: Sharmila Velamur, Fatma Arzum Simsek-Ege, Shivani Srivastava, Marsela Pontoh, Lavanya Sriram
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Publication number: 20210238287Abstract: The invention provides a medicament for use in treating a tumor in a human gastric or gastro-esophageal junction cancer patient, wherein the medicament is a LAG-3 antagonist, in particular an anti-LAG-3 antibody or a soluble LAG-3, alone or in combination with a PD-1 pathway inhibitor, in particular an anti-PD-1 antibody, and optionally one or more chemotherapeutic agents.Type: ApplicationFiled: July 25, 2019Publication date: August 5, 2021Applicant: Bristol-Myers Squibb CompanyInventor: Shivani SRIVASTAVA
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Patent number: 10991700Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.Type: GrantFiled: February 18, 2020Date of Patent: April 27, 2021Assignee: Micron Technology, Inc.Inventors: Song Guo, Sanh D. Tang, Vlad Temchenko, Shivani Srivastava
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Publication number: 20210106618Abstract: The present disclosure provides reagents and methods for treating disease using modified immune cells (e.g., T cell comprising CAR or TCR) in combination with an agent associated with induction of immunogenic cell death (ICD) and optionally further in combination with an agent that specifically binds to and/or inhibits an immune suppression component and/or an agonist of an immune stimulatory molecule.Type: ApplicationFiled: September 6, 2018Publication date: April 15, 2021Inventors: Stanley R. RIDDELL, Shivani SRIVASTAVA
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Publication number: 20210069241Abstract: The present disclosure provides compositions for treating solid tumors, including modified immune cells that specifically target tumor-associated antigens for immunotherapies, wherein expression or activity of T cell immunoreceptor with Ig and ITIM domains (TIGIT) and/or CD112R in the modified immune cells is inhibited to improve antitumor functionality of the cells. Alternatively, CD226 is overexpressed in such modified immune cells. Also provided are methods for treating solid tumors, such as tumors formed by common epithelial cancers.Type: ApplicationFiled: October 19, 2018Publication date: March 11, 2021Inventors: Stanley R. RIDDELL, Susanna Carolina BERGER, Shivani SRIVASTAVA
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Publication number: 20210030739Abstract: The disclosure is directed to methods of treating cancer in subjects with a combination of a monoclonal antibody and (R)-N-(4-chlorophenyl)-2-(cis-4-(6-fluoroquinolin-4-yl)cyclohexyl)propanamide, or a salt thereof.Type: ApplicationFiled: September 28, 2018Publication date: February 4, 2021Inventors: Paul Andrew BASCIANO, Justine Kamilah WALKER, Penny E. PHILLIPS, Li ZHU, Steven H. BERNSTEIN, James CASSIDY, Katy Lynn SIMONSEN, Alexander AZRILEVICH, Shivani SRIVASTAVA
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Publication number: 20200185389Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Inventors: Song Guo, Sanh D. Tang, Vlad Temchenko, Shivani Srivastava
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Patent number: 10593678Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.Type: GrantFiled: August 24, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventors: Song Guo, Sanh D. Tang, Vlad Temchenko, Shivani Srivastava