Abstract: A duty cycle correction circuit includes a duty cycle adjuster that is configured to receive first and second differential input signals having first and second duty cycles, respectively, that are distorted with respect to a reference duty cycle. The duty cycle adjuster is further configured to iteratively adjust the first and second duty cycles to generate first and second differential output signals having third and fourth duty cycles that are within a predefined range of the reference duty cycle, respectively. During each iteration, the duty cycle adjuster adjusts the first and second duty cycles based on correction bits that are generated based on a duty cycle detection signal that indicates whether the third duty cycle is greater than or less than the fourth duty cycle, and a lock signal that is activated when the duty cycle detection signal toggles from one logic state to another.

Abstract: Exemplary embodiments of the present disclosure are directed towards a system and methods employed for signal reception by providing programmable and switchable line terminations a universal serial bus physical layer. The system comprising at least one switching unit comprising at least two receiver pad units configured to provide programmable and switchable line terminations for signal reception in the universal serial bus physical layer. The switching unit further comprises at least one current mode logic switching unit interfaced with the receiver pad units. The system further comprises two pairs of receiver pads connected to the receiver pad units configured to receive a plurality of speed signals from at least four transmission units. The receiver pad units are enabled to route the plurality of speed signals to at least one input of a receive amplifier through the current mode logic switching unit.

Abstract: Exemplary embodiments of the present disclosure are directed towards a system and methods employed for signal reception by providing programmable and switchable line terminations a universal serial bus physical layer. The system comprising at least one switching unit comprising at least two receiver pad units configured to provide programmable and switchable line terminations for signal reception in the universal serial bus physical layer. The switching unit further comprises at least one current mode logic switching unit interfaced with the receiver pad units. The system further comprises two pairs of receiver pads connected to the receiver pad units configured to receive a plurality of speed signals from at least four transmission units. The receiver pad units are enabled to route the plurality of speed signals to at least one input of a receive amplifier through the current mode logic switching unit.