Abstract: Pipelining is included inside a register file memory. A register file memory device includes a static bitcell, and pipelined combinational logic. The combinational logic pipeline couples the I/O (input/output) node to the static bitcell. The pipeline includes multiple stages, where each stage includes a static logic element and a register element, where the operation of each stage transfers data through to a subsequent stage. The number of stages can be different for a read than a write. The multiple stages perform the operations to execute the read or write request.

Abstract: Pipelining is included inside a register file memory. A register file memory device includes a static bitcell, and pipelined combinational logic. The combinational logic pipeline couples the I/O (input/output) node to the static bitcell. The pipeline includes multiple stages, where each stage includes a static logic element and a register element, where the operation of each stage transfers data through to a subsequent stage. The number of stages can be different for a read than a write. The multiple stages perform the operations to execute the read or write request.

Abstract: A level shifter for an integrated circuit. In one embodiment, the level shifter is a bi-directional level shifter with a signal terminal located in each voltage domain that can be utilized as input or output terminal. In some embodiments, the level shifter includes transistors for cutting off the flow of current between domain power supplies when the input terminals are at a particular state. In one embodiment, only one signal line of the level shifter crosses a domain boundary.