Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: By adding multiple rows of auxiliary switches and then multiple current paths a read only memory circuit can be formed to reduce loading values when reading a specific memory cell. Therefore, the current can be increased, and the error probability of the sense amplifier can be reduced when reading a specific memory cell.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A method of fabricating a mask read-only-memory (ROM). The method includes the steps of forming a first isolated layer on the substrate having a plurality of parallel bit lines. Next, a plurality of parallel trenches are formed on the first isolated layer to define a plurality of word lines. Then, a gate oxide layer and a polysilicon are formed on bottom of the trenches in sequence to form a plurality of parallel word lines. A second isolated layer is formed according to the topography of the substrate. The second isolated layer is etched using a plurality of parallel linear mask to form tunnel regions between the neighbored bit lines in the word lines. Finally, a coding process is programmed in selected tunnel regions using a hole patterned photoresist as a mask. According to this invention, two isolated layers are defined using the parallel linear patterned photoresist, they play as protection layers between neighbor cell regions. So that the critical dimension of photolithography is enlarged.

Abstract: By adding multiple rows of auxiliary switches and then multiple current paths a read only memory circuit can be formed to reduce loading values when reading a specific memory cell. Therefore, the current can be increased, and the error probability of the sense amplifier can be reduced when reading a specific memory cell.

Abstract: A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the source node and ground of the cells is relational to the threshold voltage, so as the threshold voltage is increased, the current source voltage decreases. The threshold voltage of the dummy cell is set by a stable voltage source. The memory cell is programmed and the current source voltage of the memory cell is compared to the current source voltage of the reference cell and therefore the difference in the voltages can be used to sense convergence of the programmed cell with a target threshold level set on the reference cell. A controller is also included between the reference cell and memory cell for adjusting the threshold voltage of the dummy cell according to the gate coupling ratio of the floating gate memory cell.