Patents by Inventor Shixiang NIE

Shixiang NIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9893771
    Abstract: A frequency shift keying (FSK) demodulation component having of a sampler that receives an FSK modulated signal, samples the received FSK modulated signal, and outputs the sampled signal. The FSK demodulation component further includes a low pass filter that filters the sampled signal, and a frequency shift detector that detects shifts in frequency of the low pass filtered sampled signal. The FSK demodulation component then outputs an indication of the detection of shifts in frequency of the low pass filtered sampled signal.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: February 13, 2018
    Assignee: NXP USA, INC.
    Inventors: Zhiling Sui, Zhijun Chen, Zhihong Cheng, SHixiang Nie
  • Publication number: 20170070265
    Abstract: A frequency shift keying (FSK) demodulation component having of a sampler that receives an FSK modulated signal, samples the received FSK modulated signal, and outputs the sampled signal. The FSK demodulation component further includes a low pass filter that filters the sampled signal, and a frequency shift detector that detects shifts in frequency of the low pass filtered sampled signal. The FSK demodulation component then outputs an indication of the detection of shifts in frequency of the low pass filtered sampled signal.
    Type: Application
    Filed: August 11, 2016
    Publication date: March 9, 2017
    Inventors: ZHILING SUI, Zhijun CHEN, Zhihong CHENG, Shixiang NIE
  • Patent number: 8650327
    Abstract: A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shixiang Nie, Zhijun Chen, Zhihong Cheng
  • Patent number: 8569992
    Abstract: A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation (PWM) circuitry with individual driver PWM outputs and modulation control inputs coupled to the control outputs. There is a group of individual drivers, each one having an input coupled to one of the PWM outputs, and an output coupled to an individual driver terminal of the controller. There is common driver PWM circuitry having a common driver PWM output. A common driver having a common driver input is coupled to the common driver PWM output and a common driver output is coupled to a common driver terminal of the controller. When a coil is connected between respective driver terminals and the common driver terminal, individual PWM driver currents are supplied to the coils from the individual driver terminals and a common PWM driver current is supplied to the coils from the common driver terminal.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: October 29, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhihong Cheng, Zhijun Chen, Shixiang Nie
  • Publication number: 20130147534
    Abstract: In a master-slave D flip-flop, the master latch has first and second three-state stages and a feedback stage for positive feedback from the data outputs of the first and second three-state stages to the data input of the second three-state stage. The slave latch has third and fourth three-state stages and a feedback stage for positive feedback from the data outputs of the third and fourth three-state stages to the data input of the fourth three-state stage. Clock signals are applied from a clock signal source to the clock inputs of a clock switch element in one of the three-state stages whose clock signal is shared with another of the three-state stages, reducing the number of clock switches and clock switch power consumption. Data inverters also may be shared between a three-state stage of the master latch and a three-state stage of the slave latch.
    Type: Application
    Filed: September 6, 2012
    Publication date: June 13, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhihong Cheng, Shixiang Nie, Yang Wang
  • Publication number: 20130111099
    Abstract: A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.
    Type: Application
    Filed: September 6, 2012
    Publication date: May 2, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Shixiang NIE, Zhijun Chen, Zhihong Cheng
  • Publication number: 20110291604
    Abstract: A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation circuitry. The individual driver pulse width modulation circuitry has individual driver pulse width modulation outputs and modulation control inputs coupled to the respective control outputs. The controller has a group of individual drivers, where each one has an individual driver input coupled to a respective one of the individual driver pulse width modulation outputs, and an individual driver output coupled to an individual driver terminal of the controller. The stepper motor controller has common driver pulse width modulation circuitry having a common driver pulse width modulation output. There is also a common driver having a common driver input coupled to the common driver pulse width modulation output and a common driver output coupled to a common driver terminal of the controller.
    Type: Application
    Filed: March 15, 2011
    Publication date: December 1, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Zhihong CHENG, Zhijun CHEN, Shixiang NIE