Abstract: A calibration apparatus includes a processor, an alignment device, and an arm. The alignment device captures images in a three-dimensional space, and a tool is arranged on a flange of the arm. The processor records a first matrix of transformation between an end-effector coordinate-system and a robot coordinate-system, and performs a tool calibration procedure according to the images captured by the alignment device for obtaining a second matrix of transformation between a tool coordinate-system and the end-effector coordinate-system. The processor calculates relative position of a tool center point of the tool in the robot coordinate-system based on the first and second matrixes, and controls the TCP to move in the three-dimensional space for performing a positioning procedure so as to regard points in an alignment device coordinate-system as points of the TCP, and calculates the relative positions of points in the alignment device coordinate-system and in the robot coordinate-system.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.

Abstract: An electronic circuit for online monitoring a clock signal is provided. The electronic circuit includes a period-to-pulse converter, a pulse-shrinking block and an encoder. The period-to-pulse converter receives the clock signal outputted by a phase-locked loop, and converts each of a plurality of clock period samples of the clock signal to generate a pulse-train signal having a plurality of pulses. The pulse-shrinking block receives the plurality of pulses of the pulse-train signal, and generates a plurality of catch bits by shrinking the plurality of pulses of the pulse-train signal. The encoder outputs a minimum code denoting a minimum clock period of the clock signal and a maximum code denoting a maximum clock period of the clock signal according to the plurality of catch bits. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.

Abstract: An electronic circuit for online monitoring a clock signal is provided. The electronic circuit includes a period-to-pulse converter, a pulse-shrinking block and an encoder. The period-to-pulse converter receives the clock signal outputted by a phase-locked loop, and converts each of a plurality of clock period samples of the clock signal to generate a pulse-train signal having a plurality of pulses. The pulse-shrinking block receives the plurality of pulses of the pulse-train signal, and generates a plurality of catch bits by shrinking the plurality of pulses of the pulse-train signal. The encoder outputs a minimum code denoting a minimum clock period of the clock signal and a maximum code denoting a maximum clock period of the clock signal according to the plurality of catch bits. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.

Abstract: An electronic device includes three delay-locked loops, three dummy voter circuits, and a voter circuit. Each of the three delay-locked loops has a first input end, a second input end, an output end to maintain the phase difference between the reference clock signal received from the first input end and the intermediate clock signal output from the output end. Each of the three voter circuits is connected between the second input end and the output end of each of the three delay-locked loops to delay the phase of the intermediate clock signal by the phase difference. The voter circuit receives the intermediate clock signal from each of the three delay-locked loops, and outputs an output clock signal according to the logic of the intermediate clock signal from each of the three delay-locked loops. The phase difference compensates for the phase delay of the intermediate clock signal passing through the voter circuit.

Abstract: A system for monitoring electronic circuit configured to monitor circuit parameters of an electronic circuit is provided. The system for monitoring electronic circuit includes an observing point monitoring circuit, a system control circuit, and a signal measuring circuit. The observing point monitoring circuit includes a plurality of sensor circuits arranged in an array. The sensor circuits respectively sense the circuit parameters of a plurality of observing points in the electronic circuit. The system control circuit selects at least one of the sensor circuits to sense the circuit parameters. One of the selected sensor circuits outputs a sensing signal. The signal measuring circuit receives the sensing signal and analyzes an electrical characteristic of the sensing signal to obtain a monitoring result of the circuit parameters. A method for monitoring electronic circuit is also provided.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

Abstract: An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.

Abstract: An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.

Abstract: Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.

Abstract: A system for monitoring electronic circuit configured to monitor circuit parameters of an electronic circuit is provided. The system for monitoring electronic circuit includes an observing point monitoring circuit, a system control circuit, and a signal measuring circuit. The observing point monitoring circuit includes a plurality of sensor circuits arranged in an array. The sensor circuits respectively sense the circuit parameters of a plurality of observing points in the electronic circuit. The system control circuit selects at least one of the sensor circuits to sense the circuit parameters. One of the selected sensor circuits outputs a sensing signal. The signal measuring circuit receives the sensing signal and analyzes an electrical characteristic of the sensing signal to obtain a monitoring result of the circuit parameters. A method for monitoring electronic circuit is also provided.

Abstract: A probeless parallel test system for an integrated circuit (IC) includes an IC chip, a wireless power receiving module and a Build-In Self-Test (BIST) circuit. The wireless power receiving module is electrically connected to the IC chip. The BIST circuit is electrically connected to the wireless power receiving module and the IC chip. The wireless power receiving module, the BIST circuit and the IC chip are all formed on a wafer. The wireless power receiving module is used to provide electric power to the BIST circuit and the IC chip. When receiving the electric power, the IC chip executes a functional operation, and transmits an operation result to the BIST circuit for testing.

Abstract: Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.

Abstract: Aspects of the invention relate to techniques of testing interconnects in stacked designs for leakage defects. Logic “1” or “0” is first applied to one end of an interconnect during a first pulse. Then, logic value at the one end is captured, which triggered by an edge of a second pulse. The first pulse precedes the second pulse by a time period being selected from a plurality of delay periods. The plurality of delay periods is generated by a device shared by a plurality of interconnects.

Abstract: A multi-phase clock generation system and a clock calibration method thereof. The multi-phase clock generation system comprises an input module, a frequency division module and a control module. The input module inputs a reference clock signal with a clock period. The frequency division module according to the reference clock signal produces a phase clock signal with a frequency magnification relationship. The control module divides the phase clock signal into a plurality of clock intervals. There is a clock interval between two adjacent phase clock signals, and each of the plurality of clock intervals has a phase time delay. The control module controls a first phase clock signal of the plurality of phase clock signals to align with a last phase clock signal. The control module sequentially arranges each of the plurality of phase clock signals according to the phase time delay.

Abstract: The present invention discloses a phase-locked loop device and a clock calibration method thereof, wherein the phase-locked loop device comprises a first oscillating module, a second oscillating module, a comparison module and a control module. The first oscillating module generates a first clock signal. The second oscillating module generates a second clock signal. After comparing the first clock signal with the second clock signal, the comparison module generates a difference signal. According to the difference signal, the control module, electrically connected with the first oscillating module, the second oscillating module and the comparison module, interactively tunes the first clock signal and the second clock signal to be as close as possible.

Abstract: A method for Built-In Speed Grading (BISG) comprises a Circuit Under Test (CUT) with Built-In Self-Test (BIST) circuitry, an All-Digital Phase-Locked Loop (ADPLL), and a BISG, to automatically decide the maximum operating frequency of the CUT. The search process for this maximum operating frequency is conducted by a binary search in which the next frequency to test CUT is determined automatically by the BISG controller based on whether the CUT passes or fails the BIST session at current frequency. The maximum operating frequency the CUT can operate is narrowed down to a fine-tuning range out of a number of clock frequencies that the ADPLL can offer. The frequencies an ADPLL can offer is divided into a plurality of coarse ranges, with each of them further having a plurality of fine-tuning frequencies.

Abstract: A method for register transfer level power estimation in chip design includes the steps of: (A) parsing all possible condition branches of conditional statements in a register transfer level code, and establishing power modes inducible by each of the possible condition branches; (B) selecting a plurality of representative input vector sets from input vector sets recorded in the chip specification, and constructing linear characterization formulas corresponding to the power modes based on the selected input vector sets; and (C) calculating power values from the linear characterization formulas that correspond to the power modes, and obtaining an average power consumed by the chip from the calculated power values.