Abstract: A bus system interconnects a plurality of devices of various categories constituting an electronic music instrument apparatus for exchanging signals among the devices having unique addresses. The bus system has a serial clock line for transmission of a clock signal, and a serial data line for transfer of a data signal from a source device to a destination device in synchronization with the clock signal. The source device operates as a master to commence a communicating session such as to send the clock signal to the serial clock line and to send the data signal to the serial data line in synchronization with the clock signal. The destination device operates as a slave so as to receive the data signal based on the clock signal. The source device formulates the data signal containing a unique address specifying the destination device such that the destination device can receive the data signal exclusively from the source device.

Abstract: A bus system interconnects a plurality of devices of various categories constituting an electronic music instrument apparatus for exchanging signals among the devices having unique addresses. The bus system has a serial clock line for transmission of a clock signal, and a serial data line for transfer of a data signal from a source device to a destination device in synchronization with the clock signal. The source device operates as a master to commence a communicating session such as to send the clock signal to the serial clock line and to send the data signal to the serial data line in synchronization with the clock signal. The destination device operates as a slave so as to receive the data signal based on the clock signal. The source device formulates the data signal containing a unique address specifying the destination device such that the destination device can receive the data signal exclusively from the source device.

Abstract: In a sound source apparatus, a central processing unit is integrated in a semiconductor chip and operates in response to a primary operating clock signal for creating a control message. A tone generating unit is integrated in the same semiconductor chip and operates in response to a secondary operating clock signal for generating a musical tone according to the control message. A master clock generator generates a master clock signal having a desired frequency selected from a plurality of frequencies. A mode changer designates one of a first mode and a second mode corresponding to different operating speeds. A clock generator is provided for variably frequency-dividing the master clock signal to generate the primary operating clock signal and the secondary operating clock signal. The clock generator is responsive to the mode changer for changing a frequency ratio of the primary operating clock signal to the secondary operating clock signal between the first mode and the second mode.

Abstract: A control circuit is integrated in a semiconductor chip for controlling operation of an electronic musical instrument according to a custom program stored in an external memory so as to generate a musical tone. In the control circuit, an internal memory is formed in the semiconductor chip separately from the external memory for permanently storing a common program which is dedicated to synthesis of the musical tone while the custom program stored in the external memory is customized for the operation of the electronic musical instrument. A tone synthesizer is formed in the same semiconductor chip for synthesizing -,he musical tone when the common program is executed.