Abstract: A semiconductor storage device according to the present embodiment includes a stacked body including a plurality of first conducting films and a plurality of first insulating films alternately stacked in a first direction. A plurality of columnar bodies each include a first semiconductor part extending in the first direction in the stacked body, and a first insulator part located between the first semiconductor part and the stacked body. A transistor is located in the first direction of the stacked body. A plurality of first conductors extend in the first direction and are connected to the transistor. Three adjacent ones of the first conductors are arranged to form an equilateral triangle in a first plane orthogonal to the first direction.

Abstract: A semiconductor memory device of embodiments includes: a memory cell array including a plurality of memory cells; and a control circuit controlling an operation of each of the memory cells and including a first capacitor. The first capacitor includes: a semiconductor substrate having a first face and a second face facing the first face and including a first semiconductor region of p-type, a second semiconductor region of n-type provided between the first face and the first semiconductor region, and a third semiconductor region of p-type provided between the first face and the second semiconductor region and electrically connected to the first semiconductor region; a first electrode electrically connected to the second semiconductor region; and a first insulating film provided between the third semiconductor region and the first electrode.

Abstract: A semiconductor memory device of embodiments includes: a memory cell array including a plurality of memory cells; and a control circuit controlling an operation of each of the memory cells and including a first capacitor. The first capacitor includes: a semiconductor substrate having a first face and a second face facing the first face and including a first semiconductor region of p-type, a second semiconductor region of n-type provided between the first face and the first semiconductor region, and a third semiconductor region of p-type provided between the first face and the second semiconductor region and electrically connected to the first semiconductor region; a first electrode electrically connected to the second semiconductor region; and a first insulating film provided between the third semiconductor region and the first electrode.

Abstract: A semiconductor device includes a substrate, a first insulating layer, a second insulating layer above the first insulating layer, a void space between the first and second insulating layers, and contact electrodes extending through the first insulating layer, the void space, and the second insulating layer. Each of the contact electrodes includes a first end facing the substrate, a second end opposite to the first end, and a first width portion between the first end and the second end. The first width portion has a width in a second direction parallel to the substrate that is greater than a width of the first end in the second direction and a width of the second end in the second direction. The first width portion is within the void space.

Abstract: A semiconductor device includes a substrate, a first insulating layer, a second insulating layer above the first insulating layer, a void space between the first and second insulating layers, and contact electrodes extending through the first insulating layer, the void space, and the second insulating layer. Each of the contact electrodes includes a first end facing the substrate, a second end opposite to the first end, and a first width portion between the first end and the second end. The first width portion has a width in a second direction parallel to the substrate that is greater than a width of the first end in the second direction and a width of the second end in the second direction. The first width portion is within the void space.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer, a first gate electrode layer, a second gate electrode layer, a gate insulating film, a first interlayer insulating film, a second interlayer insulating film. The first electrode layer is separated from the substrate in a first direction. The second electrode layer is separated from the first electrode layer in a second direction. The third electrode layer is provided between the first electrode layer and the second electrode layer. The third electrode layer includes a first edge face. A second edge face of the first gate electrode layer at the second gate electrode layer side is along the first edge face.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer, a first gate electrode layer, a second gate electrode layer, a gate insulating film, a first interlayer insulating film, a second interlayer insulating film. The first electrode layer is separated from the substrate in a first direction. The second electrode layer is separated from the first electrode layer in a second direction. The third electrode layer is provided between the first electrode layer and the second electrode layer. The third electrode layer includes a first edge face. A second edge face of the first gate electrode layer at the second gate electrode layer side is along the first edge face.

Abstract: A semiconductor memory device according to an embodiment includes a connecting portion having a first region between a memory cell array and a sense amplifier portion and including transistors in the first region, one of the transistors having a first terminal electrically connected to a certain memory cell and a second terminal electrically connected to the sense amplifier portion, the connecting portion including: a first transistor group configured from transistors aligned in a first direction, the first direction being as their channel width direction; and a second transistor group configured from transistors aligned in a second direction intersecting the first direction, the second direction being as their channel width direction, and one of the first terminals of the transistors of the second transistor group being disposed more inside of the first region than one of the second terminals of the transistors of the second transistor group.