Abstract: Method and apparatus for timing modeling is described. More particularly, wire information, including wire lengths, is obtained from a routing output. Signals associated with such wire information are classified as input or output signals from an embedded core. Respective templates are automatically selected for the input signals and the output signals, respectively, at least in partial response to the wire lengths. Furthermore, timing information for the embedded core is obtained and classified according to condition, and the input signals and the output signals from the embedded core are determined to obtain rise and fall timing information for such signals.

Abstract: Method and apparatus for timing modeling is described. More particularly, sub-processes for obtaining timing information are described. Each of these sub-process is limited to a portion of a gasket module for coupling an embedded device to a host device, and each of these sub-process may be limited to a lithographic process dimension or adjusted accordingly. By dividing timing information gathering into sub-process, output from each of the sub-process may be combined with timing information provided with an embedded core to determine path delays.