Abstract: The clock generator of this invention saves a buffer memory for the data transfer interface, which has conventionally been required, when using a spectrum spread clock in circuits and devices inside a system. The clock generator can easily be applied as the operational clock in a system, and enhances the performance of the system. In the clock generator, the variable delay circuit controls the phase of the reference clock generated by an oscillator. The delay setting circuit is able to vary the setting of the control voltage to the variable delay circuit at each clock cycle, and modulates the phase of the reference clock. The phase modulation means of the delay setting circuit fluctuates the cycle of the output modulation clock to thereby spread the spectrum.

Abstract: The clock generator of this invention saves a buffer memory for the data transfer interface, which has conventionally been required, when using a spectrum spread clock in circuits and devices inside a system. The clock generator can easily be applied as the operational clock in a system, and enhances the performance of the system. In the clock generator, the variable delay circuit controls the phase of the reference clock generated by an oscillator. The delay setting circuit is able to vary the setting of the control voltage to the variable delay circuit at each clock cycle, and modulates the phase of the reference clock. The phase modulation means of the delay setting circuit fluctuates the cycle of the output modulation clock to thereby spread the spectrum.

Abstract: An inverter output circuit comprises first though third inverters connected in series. The low-potential output of the first inverter has an offset level. The input threshold voltage of the second inverter is set up at a lower level than the low-level offset potential of the first inverter as the level of supply voltage Vdd falls below a predetermined reference level. Thus, the third inverter is fixed to a predetermined condition if the supply voltage drops below the reference voltage, thereby preventing erratic operations of a load connected to the inverter output circuit caused by, for example, a power shut down and a brownout.

Abstract: An inverter output circuit comprises first though third inverters connected in series. The low-potential output of the first inverter has an offset level. The input threshold voltage of the second inverter is set up at a lower level than the low-level offset potential of the first inverter as the level of supply voltage Vdd falls below a predetermined reference level. Thus, the third inverter is fixed to a predetermined condition if the supply voltage drops below the reference voltage, thereby preventing erratic operations of a load connected to the inverter output circuit caused by, for example, a power shut down and a brownout.