Abstract: A package for holding at least one integrated circuit (IC) chip includes an IC chip, a lead frame, and a ceramic relay substrate with a wiring pattern. Respective portions of the wiring pattern are connected to the IC chip and the lead frame by respective bonding wires. The substrate includes at least one green tape with at least part of the wiring pattern thereon, and formed by printing a metal paste on the green tape and then firing it. An opening may be provided in the green tape to receive the IC chip. The assembly, which includes the IC chip, the substrate, and part of the leads of the lead frame, is sealed in a resin molding using a molding technique.

Abstract: A semiconductor package comprises an aluminum nitride substrate having a semiconductor element mounted thereon, a lead frame junctioned to the side of the aluminum nitride substrate directly contacting the mounted semiconductor element, and a ceramic sealing member junctioned to the aluminum nitride substrate so as to seal the semiconductor element. The lead frame has a coating layer of a nonmagnetic metallic material formed in a thickness of not more than 20 .mu.m on only one of the opposite surfaces of a lead frame matrix made of a ferromagnetic metal to which a bonding wire is to be junctioned. The layer of the nonmagnetic metallic material is formed by any of such thin film forming technique as the vacuum deposition technique, the spattering technique, and the plating technique. The coating layer formed on only one of the opposite surfaces of the lead frame matrix is capable of amply curbing the resistance and the dependency of inductance on frequency.

Abstract: In a ceramic lid for sealing a semiconductor device mount portion of a ceramic package substrate having a semiconductor device mounted thereon, a seal layer disposed in an outer peripheral edge portion of a lid is formed by a solder comprising 2 to 15 wt % of Bi, 2.0 to 6.0 wt % of Sn, 0.5 to 2.0 wt % of In, 0.5 to 2.0 wt % of Ag and the balance of Pb, through an Ag--Pt system underlying metallized layer. A semiconductor package comprising a semiconductor package substrate and a lid is sealed by the lid.