Patents by Inventor Shizuo Morizane

Shizuo Morizane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit
    Patent number: 6727596
    Abstract: Bump areas for signals are spread on upper and lower positions with respect to Vdd and Vss lines in an I/O buffer. Thus, the direction of routing the lines from bumps for signals to the I/O buffers is spread in two directions. A greater number of I/O buffers can be accommodated without increasing the size of a semiconductor integrated circuit.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: April 27, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsutomu Takabayashi, Shizuo Morizane
  • Integrated circuit and method of designing integrated circuit
    Patent number: 6518593
    Abstract: An integrated circuit has a functional circuit for achieving an actual operation function of the integrated circuit, and a redundant circuit for replacing a defective circuit within the functional circuit. This integrated circuit has I/O regions for signal transmission between the functional circuit and outside of the functional circuit. Each I/O region incorporates fuse boxes for switching from a defective circuit to the redundant circuit.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: February 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsutomu Takabayashi, Shizuo Morizane
  • Semiconductor integrated circuit
    Publication number: 20020130424
    Abstract: Bump areas for signals are spread on the upper and lower positions with respect to the Vdd and Vss lines in the I/O buffer. Thus, the direction of routing the lines from bumps for signals to the I/O buffers is spread into two directions. Greater number of I/O buffers can be disposed without increasing the size of the semiconductor integrated circuit.
    Type: Application
    Filed: July 31, 2001
    Publication date: September 19, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsutomu Takabayashi, Shizuo Morizane
  • Semiconductor integrated device and methods of detecting and correcting a voltage drop in an integrated circuit
    Patent number: 6377083
    Abstract: A semiconductor integrated device has a detection cell arranged in a power-supply line in the semiconductor integrated device and detecting a power-supply voltage. Further, a detection circuit detects a voltage drop of the power-supply voltage detected by the detection cell. Connection wiring connects the detection cell and the detection circuit and outputs the power-supply voltage detected by the detection cell to the detection circuit.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: April 23, 2002
    Inventors: Tsutomu Takabayashi, Kenji Kawano, Shizuo Morizane
  • Integrated circuit and method of designing integrated circuit
    Publication number: 20020031850
    Abstract: An integrated circuit has a functional circuit for achieving an actual operation function of the integrated circuit, and a redundant circuit that is used based on a changeover from a defective circuit within the functional circuit. This integrated circuit has I/O regions to carry out a signal transmission between the functional circuit and the outside. Each I/O region incorporates fuse boxes for changing over from a defective circuit to the redundant circuit.
    Type: Application
    Filed: February 1, 2001
    Publication date: March 14, 2002
    Inventors: Tsutomu Takabayashi, Shizuo Morizane