Patents by Inventor Shizuo Oguro

Shizuo Oguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030221703
    Abstract: A method of removing Ge contamination existing on a semiconductor substrate is provided. A surface of a semiconductor substrate is oxidized to convert a germanium (Ge) contamination existing on the surface of the substrate to an oxide of Ge. Thereafter, the surface of the substrate is contacted with an aqueous solution containing fluorine (F) ions. The oxide of germanium existing on the surface of the substrate is dissolved in the solution, thereby removing the Ge contamination from the substrate. Possible performance degradation of a semiconductor device to be fabricated with the substrate having the Ge contamination is prevented.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 4, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Shizuo Oguro
  • Publication number: 20010003671
    Abstract: First, there is formed a silicon film doped with impurities on a semiconductor substrate. Next, a refractory metal film is formed on the silicon film. Then, the silicon film and the refractory metal film are reacted by heat treatment to form a refractory metal silicide film.
    Type: Application
    Filed: October 14, 1998
    Publication date: June 14, 2001
    Inventor: SHIZUO OGURO
  • Patent number: 6074478
    Abstract: A flat selective silicon epitaxial thin film in which facet formation and loading effect are suppressed is grown by using a conventional LPCVD system which does not require an ultrahigh vacuum environment. Raw material gases for film formation and atomic hydrogen formed in an atomic hydrogen formation chamber 2 installed separately from a reaction chamber is introduced into the reaction chamber, at a growth temperature in the range of 750-900.degree. C. and under a reaction chamber pressure in the range of 1-30 Torr.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: June 13, 2000
    Assignee: NEC Corporation
    Inventor: Shizuo Oguro
  • Patent number: 5798544
    Abstract: Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capac
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: August 25, 1998
    Assignee: NEC Corporation
    Inventors: Shuichi Ohya, Masato Sakao, Yoshihiro Takaishi, Kiyonori Kajiyana, Takeshi Akimoto, Shizuo Oguro, Seiichi Shishiguchi
  • Patent number: 5714415
    Abstract: A method of forming a thin semiconductor film including an impurity for obtaining a conductivity includes the step of depositing a thin amorphous silicon film by chemical vapor deposition using silane as a deposition source gas at a deposition rate of at least 3 nm/minute while introducing the impurity, and the step of crystallizing the deposited thin amorphous silicon film by annealing.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: February 3, 1998
    Assignee: NEC Corporation
    Inventor: Shizuo Oguro
  • Patent number: 5464795
    Abstract: A semiconductor thin film is formed by depositing an amorphous silicon thin film and heat-treating the deposited amorphous silicon thin film. The amorphous silicon thin film is formed by a chemical vapor deposition (CVD) process while a dopant impurity is introduced, the film being not thicker than 50 nanometers. In the reaction gases used, the ratio (D/S) between the numbers S and D of atoms of silicon and dopant impurity in reaction gases is as large as 0.05.about.0.2. The polycrystalline silicon thin film thus formed is with reduced electrical resistivities.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: November 7, 1995
    Assignee: NEC Corporation
    Inventor: Shizuo Oguro
  • Patent number: 5443661
    Abstract: A silicon-on-insulator (SOI) substrate is arranged such that a polycrystalline silicon film which functions as a gettering site for heavy metals is provided on a first single crystal silicon substrate, a silicon oxide island film is partially provided in a polycrystalline silicon film, and a second single crystal silicon substrate is provided on an entire upper surface of the polycrystalline silicon film. An element isolation trench extends from an upper surface of the second single crystal silicon substrate to an upper surface of the first single crystal silicon substrate, and a silicon oxide film is buried in the element isolation trench. The SOI substrate thus constituted has a high gettering effect for heavy metals.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: August 22, 1995
    Assignee: NEC Corporation
    Inventors: Shizuo Oguro, Tatsuya Suzuki
  • Patent number: 5371039
    Abstract: A method of fabricating a semiconductor device, in particular of forming a polysilicon film on a step portion of an insulation film made by a trench or a contact hole is disclosed which includes the steps of depositing an amorphous silicon film on the step portion while doping impurities into the amorphous silicon film and carrying out heat treatment to convert the amorphous silicon film into a polycrystalline silicon film, thereby the polysilicon film on a step portion being formed.
    Type: Grant
    Filed: February 18, 1993
    Date of Patent: December 6, 1994
    Assignee: NEC Corporation
    Inventor: Shizuo Oguro
  • Patent number: 5242855
    Abstract: Disclosed is a method of forming a polycrystalline silicon film on a silicon oxide film in which the polycrystalline silicon film includes crystal grains having a large size, typically 4 micrometers, thereby permitting the resistivity of the polycrystalline silicon film to effectively be reduced. An amorphous silicon film is deposited on the silicon oxide film by using a chemical vapor deposition in which the flow rate of impurity gas remains at zero during an initial deposition, after which the flow rate is gradually increased from zero to a predetermined value during a final deposition. Thus, the amorphous silicon film comprises double layers, or an impurity unmixed region abutting the silicon oxide film and an impurity mixed region. After that, by a heat treatment, the amorphous silicon film is crystallized to form a polycrystalline silicon film. Concurrently, the impurity diffusion is accomplished.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: September 7, 1993
    Assignee: NEC Corporation
    Inventor: Shizuo Oguro