Abstract: A semiconductor package, including a first structure including a ball array region on a lower surface of the first structure and an external region completely surrounding the ball array region, the ball array region including a passive element region in which solder balls are not disposed and an edge region completely surrounding the passive element region, a first semiconductor chip on an upper surface of the first structure, a passive element in the passive element region on the lower surface of the first structure, the passive element not in the edge region on the lower surface of the first structure, and a first ball array in the edge region on the lower surface of the first structure, the first ball array including two or more first power solder balls supplying power to at least one of the passive element and the first semiconductor chip.

Abstract: A semiconductor package may include a first package including a first substrate, a first semiconductor chip mounted on the first substrate, and a second substrate on the first semiconductor chip, the first package having a center region, a first edge region surrounding the center region, and a second edge region surrounding the first edge region in a plan view, dummy balls disposed on the center region and the second edge region of the first package, connection terminals disposed on the first edge region of the first package, and a second package including a third substrate disposed on the dummy balls and the connection terminals and a second semiconductor chip mounted on the third substrate. The dummy balls may be in contact with the second substrate and may be spaced apart from the third substrate, and the connection terminals may be coupled to the second and third substrates.

Abstract: A semiconductor package includes a lower substrate that has a contact region and a non-contact region, a first upper substrate on the lower substrate, a lower device on the first upper substrate, a plurality of first solder balls between the first upper substrate and the lower substrate contact region, a plurality of capacitors between the first upper substrate and the lower substrate non-contact region, and a plurality of support blocks between the plurality of capacitors and the lower substrate non-contact region.

Abstract: A semiconductor module includes a substrate having a central region, an outer region that surrounds the central region, and a middle region disposed between the central and the outer region, a first semiconductor package mounted on the central region of the substrate, a plurality of second semiconductor packages mounted on the middle region of the substrate, and a heat radiation structure disposed on the first semiconductor package and second semiconductor packages. The heat radiation structure includes a first part that is disposed on top surfaces of the first and second semiconductor packages, a second part that surrounds the middle region, a third part that is spaced apart from the second part and surrounds the first semiconductor package, and a fourth part that connects the second part to the third part.

Abstract: Disclosed are film packages and methods of fabricating package modules. The film package includes a film substrate that includes a chip region and a peripheral region facing each other in a first direction, a plurality of output pads that are arranged in the first direction on the chip region and on the peripheral region, and a semiconductor chip on the chip region and electrically connected to the output pads. The output pads on the chip region are arranged at regular first intervals along the first direction. The output pads include a plurality of first output pads that are arranged at a first pitch along the first direction on the chip region and a plurality of second output pads on the peripheral region. The second output pads are arranged at a second pitch greater than the first pitch of the first output pads.

Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.

Abstract: A semiconductor module includes a substrate having a central region, an outer region that surrounds the central region, and a middle region disposed between the central and the outer region, a first semiconductor package mounted on the central region of the substrate, a plurality of second semiconductor packages mounted on the middle region of the substrate, and a heat radiation structure disposed on the first semiconductor package and second semiconductor packages. The heat radiation structure includes a first part that is disposed on top surfaces of the first and second semiconductor packages, a second part that surrounds the middle region, a third part that is spaced apart from the second part and surrounds the first semiconductor package, and a fourth part that connects the second part to the third part.

Abstract: A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip arranged on the first substrate, a first group of at least one solder ball arranged on a side surface of the first semiconductor chip, an interposer arranged on the first semiconductor chip and the first substrate and being in contact with the first group of at least one solder ball, and an adhesive layer arranged between the first semiconductor chip and the interposer and configured to expose at least a portion of un upper surface of the first semiconductor chip, wherein a first height from an upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than a second height of the first group of at least one solder ball.

Abstract: Disclosed are film packages and methods of fabricating package modules. The film package includes a film substrate that includes a chip region and a peripheral region facing each other in a first direction, a plurality of output pads that are arranged in the first direction on the chip region and on the peripheral region, and a semiconductor chip on the chip region and electrically connected to the output pads. The output pads on the chip region are arranged at regular first intervals along the first direction. The output pads include a plurality of first output pads that are arranged at a first pitch along the first direction on the chip region and a plurality of second output pads on the peripheral region. The second output pads are arranged at a second pitch greater than the first pitch of the first output pads.

Abstract: A printed circuit board (PCB) reducing a thickness of a semiconductor package and improving reliability of the semiconductor package, a semiconductor package including the PCB, and a method of manufacturing the PCB may be provided. The PCB may include a substrate base having at least one base layer, and a plurality of wiring layers disposed on a top surface and a bottom surface of the at least one base layer, the plurality of wiring layers defining a plurality of wiring patterns, respectively may be provided. An elastic modulus of a conductive material of one wiring pattern of at least one wiring layer from among the plurality of wiring layers may be less than a conductive material of another wiring pattern.

Abstract: A printed circuit board is provided that includes a base substrate including a pair of first edges extending in a first direction and a pair of second edges extending in a second direction, perpendicular to the first direction. A circuit region including a plurality of circuit patterns is disposed on at least one of a first surface and a second surface of the base substrate. A dummy region including a conductive dummy pattern is disposed on at least one of the first surface and the second surface. The conductive dummy pattern is separated from a boundary of the dummy region, and a maximum length of the conductive dummy pattern in the first or second direction passes through a center of the conductive dummy pattern.

Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.

Abstract: A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip arranged on the first substrate, a first group of at least one solder ball arranged on a side surface of the first semiconductor chip, an interposer arranged on the first semiconductor chip and the first substrate and being in contact with the first group of at least one solder ball, and an adhesive layer arranged between the first semiconductor chip and the interposer and configured to expose at least a portion of un upper surface of the first semiconductor chip, wherein a first height from an upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than a second height of the first group of at least one solder ball.

Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.

Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.

Abstract: Image sensor modules are provided including a lower structure, and an upper structure on the lower structure. The image sensor module further includes a semiconductor substrate in which an image sensor is formed. The lower structure includes a semiconductor chip on a region of a lower surface of the upper structure and connected to the image sensor; a reinforcing frame along an edge of the lower surface of the upper structure; and a resin molding portion between the reinforcing frame and the semiconductor chip. The reinforcing frame has a Young's modulus higher than a Young's modulus of the resin molding portion.

Abstract: A substrate structure may include a base substrate, a plurality of unit substrate regions arranged on the base substrate in one or more rows and one or more columns and spaced apart from one another, and dummy substrate regions between the unit substrate regions. In a row direction or a column direction, a first pitch between central points of two adjacent unit substrate regions among the unit substrate regions and a second pitch between central points of two adjacent second unit substrate regions among the unit substrate regions are different from each other.

Abstract: A printed circuit board (PCB) reducing a thickness of a semiconductor package and improving reliability of the semiconductor package, a semiconductor package including the PCB, and a method of manufacturing the PCB may be provided. The PCB may include a substrate base having at least one base layer, and a plurality of wiring layers disposed on a top surface and a bottom surface of the at least one base layer, the plurality of wiring layers defining a plurality of wiring patterns, respectively may be provided. An elastic modulus of a conductive material of one wiring pattern of at least one wiring layer from among the plurality of wiring layers may be less than a conductive material of another wiring pattern.

Abstract: A substrate structure may include a base substrate, a plurality of unit substrate regions arranged on the base substrate in one or more rows and one or more columns and spaced apart from one another, and dummy substrate regions between the unit substrate regions. In a row direction or a column direction, a first pitch between central points of two adjacent unit substrate regions among the unit substrate regions and a second pitch between central points of two adjacent second unit substrate regions among the unit substrate regions are different from each other.

Abstract: Provided is an electronic device which may include a first structure having a first surface, a first land region on the first surface, a second structure having a second surface facing the first surface, a second land region on the second surface, and a connection structure between the first and second structures electrically connecting the first land region to the second land region. As provided, the first land region may have a major axis and a minor axis on the first surface and the second land region may have a major axis and a minor axis on the second surface. Furthermore, the major axes of the first and second land regions may have different orientations with respect to one another.